My datasheet says about the PIR registers:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>)
Am I reading this correctly that it says that interrupts do not need to be enabled at all? That the interrupt occurs regardless if interrrupts are enabled when the event occurs?
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>)
Am I reading this correctly that it says that interrupts do not need to be enabled at all? That the interrupt occurs regardless if interrrupts are enabled when the event occurs?