Measuring the Noise Immunity in TTL and CMOS circuits

Thread Starter

SamEricson

Joined Apr 25, 2015
196
Noise Immunity
Set the AV cursors to the upper and lower threshold limits of a digital circuit.
For example, with TTL:
1. Superimpose the A REF cursor on the trace with input coupling at GND.
2. Set the A cursor for a 2.0 V readout.
3. Set the A REF cursor for 1.2 V readout, the difference between the 0.8 V
lower-threshold limit and the 2.0 V upper-threshold limit.
4. Set Input Coupling to DC and observe the relationship between the signal
and the cursors.

The signal is faulty if it changes direction between cursors or if either the high level or the low level appears between cursors.


I'm really confused on how the logic signal is faulty when it changes directions between the cursors? or the high level or low level appears between the cursors

Does this make sense to you? because I thought logic signals switch from low to high or high to low so it's going to change directions between the cursors or appear between the cursors.

I'm confused about this.
 

#12

Joined Nov 30, 2010
18,217
But what does it mean that it changes direction between the cursors?
Glad we got that cleared up. Your question is about what it means for the trace on an oscilloscope to change directions.
In the digital measurements you described, the trace on the oscilloscope goes up, away from our planet, when there is a positive input voltage and less up (down), toward out planet, when there is a less positive input voltage. Up, being the opposite of down, means the oscilloscope trace moves from the upper position to the lower position at some times. When it moves differently from what it did last, that is called changing direction.
 

Thread Starter

SamEricson

Joined Apr 25, 2015
196
how is the logic signal is faulty when it changes directions between the cursors?

The logic signal is going to change directions between the cursors, i don't understand how this is a faulty logic signal, this is normal when the logic signal changes directions.
 

eetech00

Joined Jun 8, 2013
2,320
Noise Immunity
Set the AV cursors to the upper and lower threshold limits of a digital circuit.
For example, with TTL:
1. Superimpose the A REF cursor on the trace with input coupling at GND.
2. Set the A cursor for a 2.0 V readout.
3. Set the A REF cursor for 1.2 V readout, the difference between the 0.8 V
lower-threshold limit and the 2.0 V upper-threshold limit.
4. Set Input Coupling to DC and observe the relationship between the signal
and the cursors.

The signal is faulty if it changes direction between cursors or if either the high level or the low level appears between cursors.


I'm really confused on how the logic signal is faulty when it changes directions between the cursors? or the high level or low level appears between the cursors

Does this make sense to you? because I thought logic signals switch from low to high or high to low so it's going to change directions between the cursors or appear between the cursors.

I'm confused about this.
If I understand the scenario...if the voltage input being read is > 0.8v but < 2v, then it is at an indeterminate level and won't cause a response from the digital circuit. The voltage has to be lower than 0.8v or higher than 2v to be interpreted as a logic low or logic high. So if it is > 0.8v but < 2.0v, it is faulty.
 

#12

Joined Nov 30, 2010
18,217
It is obvious that you don't have a clue what, "between the cursors" means. If you understood the setup described in the first post of this thread, you would know that the cursors were set at the upper and lower limits of the dead band of the logic family. The logic family characteristics define what voltage is allowed to be called, "high" and what voltage is allowed to be called, "low". The area between the cursors is not allowed to cause a change in the outputs in that family, so a change between the cursors proves there is a defect.
 

Thread Starter

SamEricson

Joined Apr 25, 2015
196
If I understand the scenario...if the voltage input being read is > 0.8v but < 2v, then it is at an indeterminate level and won't cause a response from the digital circuit. The voltage has to be lower than 0.8v or higher than 2v to be interpreted as a logic low or logic high. So if it is > 0.8v but < 2.0v, it is faulty.
Yes, I understand this , but how is this testing Noise Immunity in a logic TLL or CMOS circuit?

If the logic signals are changing between 0.8 and 2 volts this is noise immunity?
 

eetech00

Joined Jun 8, 2013
2,320
Yes, I understand this , but how is this testing Noise Immunity in a logic TLL or CMOS circuit?

If the logic signals are changing between 0.8 and 2 volts this is noise immunity?
That's a good question...

Edit:
If it helps, here is an excerpt from a Fairchild App note 375. It is from the section entitled "understanding Noise"

"To quantify these noise parameters, first define “noise immunity”:
a device’s ability to prevent noise on its input from being
transferred to its output. More specifically, it’s the amount
of voltage that can be applied to an input without causing the
output to change state."
 
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