I’m trying to understand microcontroller (MCU) architectures and their classifications. Could you please confirm if my understanding below is accurate or if I’m missing anything?

My Understanding:

1. Architecture Types:
   • Harvard Architecture: Separate buses for code and data memory (e.g., AVR, PIC, most ARM Cortex-M like STM32).
   • Von Neumann Architecture: Shared memory for code and data (e.g., 8051).
2. Data Width Classification:
   • 8-bit (e.g., 8051, ATmega328P in Arduino Uno, PIC16/18).
   • 16-bit (e.g., MSP430, some PIC24).
   • 32-bit (e.g., ARM Cortex-M series, ESP32).
3. Application-Based Grouping:
   • General Purpose
   • Automotive
   • Wireless/ IoT
   • Industrial
   • Ultra-Low Power

Are there any inaccuracies or key points I’ve overlooked? For example, do modern MCUs still strictly follow Harvard/Von Neumann, ? Also, are there other important classifications (e.g., core type, RISC vs. CISC)?

 

I’m trying to understand microcontroller (MCU) architectures and their classifications. Could you please confirm if my understanding below is accurate or if I’m missing anything?

My Understanding:

1. Architecture Types:
   • Harvard Architecture: Separate buses for code and data memory (e.g., AVR, PIC, most ARM Cortex-M like STM32).
   • Von Neumann Architecture: Shared memory for code and data (e.g., 8051).
2. Data Width Classification:
   • 8-bit (e.g., 8051, ATmega328P in Arduino Uno, PIC16/18).
   • 16-bit (e.g., MSP430, some PIC24).
   • 32-bit (e.g., ARM Cortex-M series, ESP32).
3. Application-Based Grouping:
   • General Purpose
   • Automotive
   • Wireless/ IoT
   • Industrial
   • Ultra-Low Power

Are there any inaccuracies or key points I’ve overlooked? For example, do modern MCUs still strictly follow Harvard/Von Neumann, ? Also, are there other important classifications (e.g., core type, RISC vs. CISC)?

Some are described as load-store architecture and others as register-memory, there also 64bit MCUs now too. There are plenty of gurus here too who have insights, I'd say your breakdown was very good.

 

I’m trying to understand microcontroller (MCU) architectures and their classifications. Could you please confirm if my understanding below is accurate or if I’m missing anything?

My Understanding:

1. Architecture Types:
   • Harvard Architecture: Separate buses for code and data memory (e.g., AVR, PIC, most ARM Cortex-M like STM32).
   • Von Neumann Architecture: Shared memory for code and data (e.g., 8051).
2. Data Width Classification:
   • 8-bit (e.g., 8051, ATmega328P in Arduino Uno, PIC16/18).
   • 16-bit (e.g., MSP430, some PIC24).
   • 32-bit (e.g., ARM Cortex-M series, ESP32).
3. Application-Based Grouping:
   • General Purpose
   • Automotive
   • Wireless/ IoT
   • Industrial
   • Ultra-Low Power

Are there any inaccuracies or key points I’ve overlooked? For example, do modern MCUs still strictly follow Harvard/Von Neumann, ? Also, are there other important classifications (e.g., core type, RISC vs. CISC)?

Why are you asking questions over and over that you already have the answers to? Looks like new BOT testing.

 

Why are you asking questions over and over that you already have the answers to? Looks like new BOT testing.

I only have a rough understanding of this, and I wanted to confirm with experts. Forums like this have engineers who’ve actually worked with these architectures—they can clarify real-world quirks that tutorials don’t cover.

 

Why are you asking questions over and over that you already have the answers to?

Why are you talking to an AI?

 

Why are you talking to an AI?

 

If you had asked this question 30 years ago, give or take a few years, additional subdivisions would be the way the firmware was stored: UV-EEPROM, OTP, mask ROM.

Thank heavens nowadays we have Flash Memory!! For those of us who had to use those primitive firmware storage mechanisms, the absolutely worst terror was to find a new firmware bug, when an order had already been placed for 100k masked processors!!

 

If you had asked this question 30 years ago, give or take a few years, additional subdivisions would be the way the firmware was stored: UV-EEPROM, OTP, mask ROM.

Thank heavens nowadays we have Flash Memory!! For those of us who had to use those primitive firmware storage mechanisms, the absolutely worst terror was to find a new firmware bug, when an order had already been placed for 100k masked processors!!

More like 50+ years ago, and the turnaround time for a fix to a masked ROM chip was 6 weeks.

 

More like 50+ years ago, and the turnaround time for a fix to a masked ROM chip was 6 weeks.

Hmmm. The last masked ROM I wrote code for was in 1992 -- for a National Semi COP420.

 

Still using UV-EEPROM for ladder logic control programming on some old but still operational semi equipment. Still have the CRT degaussing coil too. That Flash Memory's granddaddy is still on the job.

Hell, tubes are still being used in HV power supplies.

 

View attachment 350641

Still using UV-EEPROM for ladder logic control programming on some old but still operational semi equipment. Still have the CRT degaussing coil too. That Flash Memory's granddaddy is still on the job.

Hell, tubes are still being used in HV power supplies.
View attachment 350644

I got the same Pace solder station!

 

I got the same Pace solder station!

Most of the shop was setup by old Navy techs. That Pace station was the training standard at repair school, so naturally, we use what we know well.

I gave it and most of the old stuff away to another group when I upgraded the rework station to METCAL.

 

Most of the shop was setup by old Navy techs. That Pace station was the training standard at repair school, so naturally, we use what we know well.

I gave it and most of the old stuff away to another group when I upgraded the rework station to METCAL.

Been using mine for 25 years. Had to replace a few parts over the years, but otherwise they hold up real well.

 

More like 50+ years ago, and the turnaround time for a fix to a masked ROM chip was 6 weeks.

For a factory consuming over 100k devices per month, running those 6 weeks on OTPs which were more expensive and required re-routng to an external vendor for programming, plus the new mask’s costs, plus scrapping the inventory of now worthless masked devices, plus reworking units on the warehouse and sometimes in the field, that would run well over half a million dollars, in 1990 dollars.

 

For a factory consuming over 100k devices per month, running those 6 weeks on OTPs which were more expensive and required re-routng to an external vendor for programming, plus the new mask’s costs, plus scrapping the inventory of now worthless masked devices, plus reworking units on the warehouse and sometimes in the field, that would run well over half a million dollars, in 1990 dollars.

We made sure to make fewer mistakes in those days.

 

For a factory consuming over 100k devices per month, running those 6 weeks on OTPs which were more expensive and required re-routng to an external vendor for programming, plus the new mask’s costs, plus scrapping the inventory of now worthless masked devices, plus reworking units on the warehouse and sometimes in the field, that would run well over half a million dollars, in 1990 dollars.

In 1971 there was no such thing as an OTP. This was even before UV erasable devices. OTP's were several more years in the future.

 

PROM was invented in 50's and used in the 50's for the military. We had them in digital security gear made in the 60's for crypto codes.

 

PROMS were used on Data General Nova minicomputer CPUs as early as 1970.