How can I determine the maximum frequency at which a digital IC can operate?

I often find that I'm looking at a datasheet, wondering if a certain IC can receive and drive a signal at my desired frequency. I'll get a spec that a customer needs a signal of a certain voltage level at a certain frequency, and it can be frustrating sourcing parts when it's not clear if they can do the job. Unfortunately, I never have time to breadboard, so I need to make decisions based on the datasheet and be conservative in my designs. I'd like to know if there's a way to tell the max frequency from the datasheet.

Some datasheets do include a max frequency or bps. Some include a graph of power supply current versus frequency, so I can infer that the graphed frequencies are possible. These are not a problem.

Many datasheets only include propagation delay, which I'm not completely convinced is what I need. I could take the largest propagation delay that I would expect (based on temp, supply voltage and load capacitance), and figure that the Fmax = 1/(2*tpd), but I don't think that's necessarily correct. I think the max frequency could be either lesser or greater than that. Even though a signal edge takes a certain amount of time to propagate through an IC, that doesn't mean the IC has to wait that long for the next signal to start propagating through. Likewise, if a signal edge has finished propagating through an IC, that doesn't necessarily mean that the input is ready for the next one. But propagation delay currently seems to be my best hint, so that's what I use (with a good margin for error).

Also, I'm not always concerned with the amplitude of the signal produced. I realize that at higher frequencies, the signal will attenuate. What I want to know is, if there's a healthy signal on the input, up to what frequency will there be any signal on the output? I think this removes the effect of load capacitance, but not temperature or supply voltage.

If an example helps, you can use the 74LCX86. I've driven it at 100MHz, but I don't know how much faster I could trust it to go.

Thanks. This isn't a current problem. It just comes up repeatedly, so I'd like to know how to handle it next time.

 

Propagation delays and maximum operating frequency where applicable must be specified in the manufacturer's data sheet.
This is required since it is the basis for correct engineering design. Also this is the manufacturer's guarantee.

Testing a circuit on a breadboard does not guarantee reliable operation for all devices. In many cases you can exceed the data sheet specifications but you are setting yourself up for system failure somewhere down the line. Stay within the manufacturer's specs.

Propagation delay and not maximum frequency will be quoted for gates.
Maximum frequency (actually, minimum max operating frequency) will be quoted for clocked logic circuits.

 

Can you show us an example of a datasheet which lacks the appropriate information. I've spent half a century designing hardware and never encountered your problem.

 

external 100 MHz are quite creepy to handle I could imagine.

 

In addition to what has been pointed out about not relying on your design being able to achieve the performance that a particular instantiation happened to result in, you also have to contend that, with today's parts, you will pretty much never get anywhere close to maximum performance in a breadboarded implementation. Even halfway decent PCB layout will let you far surpass the speed you can achieve on a breadboard.

Also, what you are really wanting to determine is the max speed at which you can run a design, not a particular digital part. You need to identify the critical path in the design and focus on that. The maximum operating frequency of the circuit is going to be determined by the maximum propagation delay of the critical path, taking into account the set-up and hold time requirements of the clocked elements as well.

 

Can you show us an example of a datasheet which lacks the appropriate information.

My example is the 74LCX86. Here’s the Fairchild datasheet. I can’t say that it lacks the appropriate information. I can say that, looking at this datasheet, I personally can’t tell the maximum operating frequency under any condition. My question is, how can I determine a maximum operating frequency?

I’ve used this part because it can be powered by 2v to 3.6v, but it accepts a 5v input regardless. There may be parts outside the 74LCX family that can do this, but it can be hard to find one that lists its max frequency. I can look, but in the situation I often find myself in, I have a deadline, and prefer not to waste time looking for a part that might not exist, especially when I have a part that would do the job if its max frequency is adequate.

 

Propagation delays and maximum operating frequency where applicable must be specified in the manufacturer's data sheet.
This is required since it is the basis for correct engineering design. Also this is the manufacturer's guarantee.

Testing a circuit on a breadboard does not guarantee reliable operation for all devices. In many cases you can exceed the data sheet specifications but you are setting yourself up for system failure somewhere down the line. Stay within the manufacturer's specs.

Propagation delay and not maximum frequency will be quoted for gates.
Maximum frequency (actually, minimum max operating frequency) will be quoted for clocked logic circuits.

Propagation delay, and not max freq, being quoted for gates, is great info. Thanks.

All points about breadboard testing, and observations of actual behavior, not guaranteeing future performance are points well made.

But if a gate is not going to tell me what its max frequency is, and I can’t trust what I see the part do, how can I tell how fast the part will run?

My example is the 74LCX86. The datasheet says the max propagation delay is 6.5ns (when powered by 3.3v and other conditions are met). It quotes no maximum frequency. I’ve seen it run at 100MHz, but there is no guarantee that every future part I try will do this. Fairchild could even change how they make the part, keep it in spec, and yet make it so it won’t operate as I’ve seen it operate in the past. Nothing I can see in the spec guarantees that it will run at 100MHz. In fact, nothing I can see in the spec guarantees that it will run at a pokey 1MHz or even lower.

I know this is ridiculous, but what (beyond common sense) guarantees that they won’t make a part with a 6.5ns max propagation delay, but it can only toggle every 1000ns. I see nothing in the spec guaranteeing any frequency at all. The reasons I’m sure it operates at 1MHz are common sense and experience, but we’re saying that’s not good enough. We need a guarantee from the datasheet.

Perhaps what I’m looking for would be in an “Understanding Datasheets” app note. There may be some implicit assumptions spelled out elsewhere. I’ll look for that next.

 

Like I said, max frequency is not relevant for a gate. Propagation delay is relevant.
A change in the input propagates to a change in output. What you want to know is what is the maximum delay between the change in input and the change in output.

 

Also, what you are really wanting to determine is the max speed at which you can run a design, not a particular digital part. You need to identify the critical path in the design and focus on that. The maximum operating frequency of the circuit is going to be determined by the maximum propagation delay of the critical path, taking into account the set-up and hold time requirements of the clocked elements as well.

I do want the max speed I can run my design, but I think that means I want the max speed for each of my parts. The lowest max speed of any of my parts will set the max speed for my design (provided my layout also supports this speed). The chain is as strong as its weakest link. So what I need to know is, for each part, if it gets a clean input at a certain frequency, will it drive that frequency at its output?

If I’m worried about a chip’s max frequency, I tend to be out of the domain of identifying the critical path. If I’m running something >20MHz, it’s usually a free running clock that I need just need to fan out and then convert to the appropriate voltage. But all of this is just my own personal circumstance, which may be counter to what certain ICs are designed for.

 

My example is the 74LCX86. Here’s the Fairchild datasheet. I can’t say that it lacks the appropriate information. I can say that, looking at this datasheet, I personally can’t tell the maximum operating frequency under any condition. My question is, how can I determine a maximum operating frequency?

I’ve used this part because it can be powered by 2v to 3.6v, but it accepts a 5v input regardless. There may be parts outside the 74LCX family that can do this, but it can be hard to find one that lists its max frequency. I can look, but in the situation I often find myself in, I have a deadline, and prefer not to waste time looking for a part that might not exist, especially when I have a part that would do the job if its max frequency is adequate.

You are drawing a number of erroneous conclusions here. The first is that each part of a design must be able to run at the fastest speed of any part in the design. That is manifestly not the case. In your example of using a gate to distribute a clock signal you are asking the wrong question. The question is not how fast a signal can I put through the gate; it is how much capacitative load can I drive without distorting the clock signal. This is a very different thing. Capacitative load depends on things which are unknowable from a jig or test fixture. At extreme frequencies, above say 50 MHz., the layout of your transmission lines and their terminations will have much more effect that any internal properties of the individual components.

At these frequencies above 50 MHz.,the "gates" should actually be inside an FPGA to keep the path lengths short.

In any case in answer to your question about the specific part, you may wish to consider the frequency dependent power dissipation. Running at a lower Vcc than 5 volts is helpful. The part will pass higher frequencies than indicated by propagation delay, but at some frequency the gate will spend so much time in the linear region that it will literally cook itself. Define the linear region as [0.25, 0.75]Vcc and limit yourself to no more than 33% of the time in that range.

 

Mr Chips
Like I said, max frequency is not relevant for a gate. Propagation delay is relevant.

I do want the max speed I can run my design, but I think that means I want the max speed for each of my parts. The lowest max speed of any of my parts will set the max speed for my design (provided my layout also supports this speed). The chain is as strong as its weakest link.

You should listen to Mr Chips and others.

Your current designs may only include one simple straightforward serial path, but most logic applications have many (parallel or sub parallel)paths.

The propagation delay is absolutely vital in these cases since a 'short' path with a short prop delay may result in a pulse appearing too soon relative to another that has a longer path through the circuit.

Further at 100Mhz + you need to consider the time of passage between chips and even between the pins of the same chip in the circuit layout.

You should Google "Race Conditions"

I do not have a pretty multi channel scope to demonstrate, perhaps another who deals in this all the time could post a pic or two to demonstrate?

 

What is the relationship between propagation delay and max frequency? Max frequency = 1 / (path delay), where path delay is the sum of the propagation delays over the longest signal path through a circuit. In the case of a single gate, path delay = propagation delay. Hence, for a single gate, max frequency is the inverse of the propagation delay. Note however, the addition of additional gates will reduce max frequency, as studiot has explained so well

 

The question is, is Max freq for a single gate really 1/propagation delay? When the input signal exceeds that limit, will the output stop toggling, or will it simply be still toggling propagation delay later? Is the line drawn at exactly that number?
With simple logic gates I don´t see any reason why these two should be related. I agree that Tpd is the important figure in a system design, but with single gates I dont see that.

 

The question is, is Max freq for a single gate really 1/propagation delay? When the input signal exceeds that limit, will the output stop toggling, or will it simply be still toggling propagation delay later? Is the line drawn at exactly that number?
With simple logic gates I don´t see any reason why these two should be related. I agree that Tpd is the important figure in a system design, but with single gates I dont see that.

This is especially true of optos used in fiber optic communication. They will pass 50 MHz signals with several hundred microseconds of delay. We could not use them in a CAN application at 500 kHz because the delay was too much for the CAN protocol.

 

The question is, is Max freq for a single gate really 1/propagation delay? When the input signal exceeds that limit, will the output stop toggling, or will it simply be still toggling propagation delay later? Is the line drawn at exactly that number?
With simple logic gates I don´t see any reason why these two should be related. I agree that Tpd is the important figure in a system design, but with single gates I dont see that.

For me, this is part of the question. The other part is, could the max frequency for a single gate be lower than 1/propagation delay? If someone could just rule this out, perhaps explaining why, it would answer part of the question, giving me part of what I came here for. As I said before, I don't know that a gate input is ready to receive its next toggle simply because the last one has completed propagation.

A side question: Is it really 1/propagation delay that we should be comparing the Max freq? I tend towards 1/(2*Tpd), off by a factor of 2. I measure a clock period from a rising edge to the next rising edge. Is it standard in this context to measure from rising edge to falling edge, double data rate style?

Thank you, kubeek, for your focus on the question. I appreciate the effort that everyone has given on this, but it is notable how most responses explain why the question is wrong or unnecessary. I know what my question is and would value an answer.

I understand that the scenario I've described is not a typical use of a logic gate. I understand race conditions (at least at a sophomore level) and they do not apply to my situation. I understand that if a gate succeeds in driving a signal at a high frequency, I must still consider capacitive loading, layout, etc... I understand that Propagation Delay is typically what's relevant for a gate, but in this case I want more information if possible.

I reiterate that I appreciate the responses I've received. They contain good information, just not an answer yet.

 

I do want the max speed I can run my design, but I think that means I want the max speed for each of my parts. The lowest max speed of any of my parts will set the max speed for my design (provided my layout also supports this speed). The chain is as strong as its weakest link. So what I need to know is, for each part, if it gets a clean input at a certain frequency, will it drive that frequency at its output?

If I’m worried about a chip’s max frequency, I tend to be out of the domain of identifying the critical path. If I’m running something >20MHz, it’s usually a free running clock that I need just need to fan out and then convert to the appropriate voltage. But all of this is just my own personal circumstance, which may be counter to what certain ICs are designed for.

Consider this simple example using some made up numbers.

I have a 74WB74 (the WB family is made up, so I get to make up the numbers to make the math easy) dual D-type FF that has a 2 ns setup time and a 3 ns propagation delay. I now connect two of these so that the Q' output of each goes to the D input of the other. How fast can I make this run without violating the spec? From the rising edge of the clock it will take 3 ns for the new data to make it to the outputs. The data has to be at the input no later than 2 ns prior to the next rising clock edge, so I can't provide another clock edge any sooner than 5 ns after the previous one, hence my max speed is 200 MHz. This is assuming negligible propagation time along the routing between gates. Most instantiations will actually work at higher clock rates than this, but this is the fastest clock rate that will not violate the specs.

Now let's modify the design and put a 74WB86 XOR gate in there with one input coming from the Q' output of the first DFF and the other input coming from a switch that will normally be held static in one state or the other. The XOR gate has a prop delay of 3 ns. Note that I'm only putting one of these gates between the first and second DFF and that I'm not changing anything about the signal from the second DFF back to the first. So now I have two paths. The one that is unchanged still limits the circuit to no more than 200 MHz, but the one that did change introduced an additional 3 ns on top of the 5 ns that was already there, so now I have a path that must allow for 8 ns between clocks, limiting my speed to 125 MHz. Now what happens if I decide to buffer the Q' output of the first DFF with a series chain of six NOT gates from a 74WB06 hex inverter in which each inverter has a propagation delay of 2 ns? Those six inverters just added another 12 ns of delay to the 8 ns giving me a total of 20 ns and lowering my max speed to 50 MHz. So even though I added components that were significantly faster than any of the components in the existing design, it significantly reduced the max speed of the overall circuit.

What if I then decide to use the Q output of the second DFF (which, remember, was going directly back to the D input of the first) by using a really slow NOT gate (perhaps it is driving a heavy LED load or something) that has a propagation delay of 12 ns? The total prop delay along this path is 17 ns (3 ns for the DFF, 12 ns for the NOT gate, and 2 ns to allow for the setup time). This is less than the delay of the other path, so it is not the critical path and therefore does not affect the speed of the overall design even though it contains, by far, the slowest part in the design.

Do you begin to see how the individual gates only matter to the degree to which they contribute to the propagation delay along the critical path. So unless you circuit consists ONLY of a single layer of gates, it is meaningless to talk about a maximum frequency that a gate can be run at.

 

The question is, is Max freq for a single gate really 1/propagation delay? When the input signal exceeds that limit, will the output stop toggling, or will it simply be still toggling propagation delay later? Is the line drawn at exactly that number?
With simple logic gates I don´t see any reason why these two should be related. I agree that Tpd is the important figure in a system design, but with single gates I dont see that.

It has to do with circuit implementation details and glitch energy. Let's say that you have a signal that is LO and that then goes HI for 1 ns before going LO again and let's say that the circuit has a propagation delay of 5 ns. Will you see a roughly 1 ns glitch on the output (assuming that the output would have changed had the change in input been long)? Maybe. Or it might not be passed through at all. This is why for non-clocked signals you will often see minimum signal width requirements in the timing specs. Any signal short than that may not be passed on.

In using the propagation delay to come up with a speed, what you are really doing is assuming that the output is being feedback to become the inputs, such as for a ring oscillator.

 

Wbahn: imagine instead of a complex system such as your example something much simpler. For example a level-shifter feeding a clock input of a fast counter. Lets say the counter works up to 250MHz, but the only data you can find for the level shifter is that the propagation delay is 6ns. Is the level shifter going to keep up with 250MHz data rate or not, nevermind it being delayd 6ns as the delay doesn't matter in this case. How do you tell?

In verilog course there were explained two kinds of delay that can be modeled in digital design. Those were transport and inertial delays, where transport delay is similar to a transmission line so that everything gets from input to output with some delay, but no level transition gets lost however fast it may be.
Inertial delay can be seen as an RC filter, such that narrow pulses will be filtered out and never reach the threshold required for the gate to toggle.

My view of this is that every gate will basically boil down to an RC low pass at high frequencies, so the intertial delay model would be appropriate. Nevertheless the max frequency could still easily be twice 1/Tpd and you cant really tell.

 

Do you begin to see how the individual gates only matter to the degree to which they contribute to the propagation delay along the critical path. So unless you circuit consists ONLY of a single layer of gates, it is meaningless to talk about a maximum frequency that a gate can be run at.

I see how, in your example, it's the total propagation delay along the critical path that matters. You're clocking in 'data'. You've got a nice defined setup time. The clock has to wait for the data. But that's not my situation.

I typically have a free running clock that I need to get from one place to another, typically through a few ICs for fan out and voltage translation. It's typically not even in synch with anything. So all that I care about, for each IC, is whether it will it receive the signal from the previous IC, and drive it to the next IC.

Even if you can't imagine why, I really want to know how to determine the max frequency for one gate. If you don't know the answer, that's fine.

Thank you for your thoughtful post. If you want to throw up your hands and say "This guy will never get it", you've more than earned that right.

 

I believe most level shifter circuits are likely to be dominated by inertial delay behavior, so I would not expect such a device with a 6 ns prop delay to work particularly reliably in a circuit that nominally calls for something with less than 2 ns.

Keep in mind that inertial and transport delays are neither either/or nor are they absolute. Most real circuits exhibit a bit of both and generally shift behavior from transport to inertial as the signal glitch energy drops.

Probably the best way to tell -- and it is far from guaranteed that you will get the info you need -- is to query the manufacturer of the part. Don't ask generic questions when you do. Ask a very specific question such as:

I am using your part #FRED (which has a propagation delay of 6 ns under the test conditions in the datasheet) to translate a clock signal from 2.5V to 3.3V in order to drive the clock input of a #SUE (data sheet attached). My input signal to the #FRED will be a square wave at 250 MHz coming out of a #BOB (datasheet attached). I am concerned that the #FRED will not be able to adequately pass a clock signal of this speed, but can't determine from the datasheet whether this is the case or not. Could you please advise and, if it can't, could you recommend a potential solution?