I need to do a tehnology mapping (group gates and flip flops) given a D ff and a MUX. Now I know what FPGAs mean and I understand I need to group them so that they "fit" in the given cell. But if I have only a D ff in my cell doesn't that mean I can group only the gates that are connected to the ff? A little help would be great cause I tried looking over some tutorials but didn't understand much. What I managed to understand is we have 128 entries and the cell asks for 16 therefor we need to have 8 groups 128:16.


https://i.stack.imgur.com/pSZds.jpg

 

Hello,

You can upload images to the forum directly, instead of posting them on some image hosting site.



I also changed the contrast a bit.

Bertus