I am certain I found a schematic somewhere for a BJT based priority encoder (i.e. a cell where a high input turns low all the preceding stages) but now I can't find it. The circuit I am thinking of has two inputs and two BJTs. Can anyone confirm I didn't dream it? And also share a link

 

I found a schematic somewhere for a BJT based priority encoder (i.e. a cell where a high input turns low all the preceding stages) but now I can't find it. The circuit I am thinking of has two inputs and two BJTs.

I've never seen such a circuit.

Did it look something like this (that I just threw together)?

Input B is the most significant bit (MSB), hence LED1 represents the MSB. D1 insures that Q2 will be off when Q1 is on.

This is the logic diagram:

EDIT: cleaned up logic diagram.

B represents MSB and the LED on the left is MSB. Don't obsess over the lack of resistors and loading the output of the AND gate. That's just how the simulator I use works...