Ok , I am using dev c for my IDE.
I am trying to use my own built make file but it is not working

I have tried tabs , spaces I am still getting *** missing seperator.
As well as

Anybody see any problems or where I should have tabs?

CC = gcc
LINK = ld
INCS = 
LIBS =
RES  =
SOURCE = $(wildcard *.c)
OBJ = $(wildcard *.o)
BIN = kernel.bin
RM = rm -f
CFLAGS = $(INCS) -Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions -nostdinc -fno-builtin -c
LFLAGS = -T link.ld
all:
$(CC) $(CFLAGS) $(SOURCE) 
all:
$(LINK) $(LFLAGS) $(OBJ) -o $(BIN)
.PHONY: all all-before all-after clean clean-custom
clean: clean-custom
 ${RM} $(OBJ)

 

General practice (and it depends on the flavor of make) is to include a tab character on every line of a recipe. Your makefile doesn't appear to have some needed tabs, but I can't tell for sure, since the board's code thingy probably just treats all whitespace except \n the same.

I suggest you learn to use pattern rules or (obsolete) suffix rules too (see e.g. the GNU make manual). They can save you lots of build time, especially on bigger projects.

Do you know you have two "all" targets in your file?

When people begin to start using make, I recommend that they start with an absolutely minimum makefile. Use something like:

all:
        gcc -o mypgm a.c b.c

Get that working, then start adding more targets/recipes and variables. Run make again after each change to make sure you haven't broken anything. Then start adding pattern rules, variables, conditional stuff, etc.

I also recommend getting rid of implicit rules if you're using something like GNU make, as it can cause problems that can take a while to debug. I want my makefile to do only what I tell it to.

I use GNU make and always invoke it with the options --warn-undefined-variables --no-builtin-rules.