Low Offset Voltage Follower

Thread Starter

Oreoluwa Adesina

Joined May 11, 2019
3
I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range.

I have a few constraints for this task:


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- I can use nmos, pmos and pmos4 but cant use nmos4 as the fabrication process does not support seperate bulks for NMOS transistors.

- I cannot use controlled sources e.g (vcvs,vccs,ccvs,cccs) except when calculating Voffset

- I can only use one Vdc for Vdd and one Vdc for Vin and use only idc for biasing

- Use at least 100nA bias current in all transistors


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So far I have tried adding cascodes to the circuit to reduce this offset voltage but no luck. I would really appreciate it if someone could point me in the right direction regarding this task.
 

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ericgibbs

Joined Jan 29, 2010
9,575
hi OA.
Welcome to AAC.
As your question is part of Homework, I will move your Thread to the Homework Forums.
E
 
Last edited:

crutschow

Joined Mar 14, 2008
24,405
I would think the circuit offset would depend greatly on the offset difference between two identical sized MOSFETs the selected process can achieve.
Or are you assuming a perfect match?
 

MrAl

Joined Jun 17, 2014
7,191
I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range.

I have a few constraints for this task:


----------


- I can use nmos, pmos and pmos4 but cant use nmos4 as the fabrication process does not support seperate bulks for NMOS transistors.

- I cannot use controlled sources e.g (vcvs,vccs,ccvs,cccs) except when calculating Voffset

- I can only use one Vdc for Vdd and one Vdc for Vin and use only idc for biasing

- Use at least 100nA bias current in all transistors


----------

So far I have tried adding cascodes to the circuit to reduce this offset voltage but no luck. I would really appreciate it if someone could point me in the right direction regarding this task.
Hello Morty,

I can give you a hint that the apparent input offset in a regular ideal inverting amplifier with negative feedback is:
OS=(a*E1)/(A+a+1)

where 'A' is the open loop gain and 'a' is the gain of the stage, and E1 is the input DC voltage.

and the output offset is
OOS=OS*/(a+1)

Looking at that first one, we can see that the higher the open loop gain the lower the OS and thus the lower the output offset too.

See what you can do with that.
 
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