<snip> why am I stuck on this problem? (Cause it is interesting though completely impracticable!)

The full adder can get a little more optimized from 15 ICs down to 8 by taking advantage of the Carry In bit; meaning an adder can add three bits together, not just two. Thus the first stage of 8 adders adding pairs can be reduced to 4 adders adding triplets. The left over 4 bits can get added in to higher stages. Delay stays the same.

Every picture tells a story:

All adder stages are identical, I just expanded the last stage to show all 5 output bits. All unused inputs to to zero (ground). The most significant bit (S4) of the last adder is the carry out.

Geo: Using a ROM as a logic device is a very old school trick, but it started the path that eventually gave us FPGAs.

 

What do you mean by identical?

The schematic doesn't depict them, but the 1bit adder has an output C for the Carry-out and the output S for the Sum.

I 'd also like to use another adder to sum up bits 1, 2 and 3 in the first column.

Before I explain my revision, I 'd like to remind that when we sum two, say, 3bit numbers A2A1A0 and B2B1B0, we can sum the 0 order digits and the result will be another 2bit number C1C0. The final result will contain C0 as it is, because there is no other 0 order digit to sum it with.
Similarly, we can add A1, B1 and C1 and take a 2bit result D2D1. The least significant bit D1 will be the 1st order digit of our final result because there is no other 1st order digit to sum.
The same goes for higher order digits. We sum the equal order digits together until we run out of sums.

I find it a bit hard to draw that specific schematic, it being unconventionally dissimilar to a classic circuit, so I will describe it in words so you can draw it yourself.

That said, each 1bit adder has a letter assigned to it. It also has three inputs and two 1-bit outputs for carry and sum that will have the number of the order of the digit they contain.

Let's start:

The input has the bits I0-I15.
Full adder A: Input :I15,I14,I13 Output :A1,A0
Full adder B: Input :I12,I11,I10 Output :B1,B0
Full adder C: Input :I09,I08,I07 Output :C1,C0
Full adder D: Input :I06,I05,I04 Output : D1,D0
Full adder E: Input :I03,I02,I01 Output :E1,E0
Full adder F: Input :A0,B0,C0 Output :F1,F0
Full adder G: Input : D0,E0,I00 Output :G1,G0
Full adder H: Input :A1,B1,F1 Output :H2,H1
Full adder I: Input :C1,D1,E1 Output :I2,I1
Full adder J: Input :F0,G0,GROUND Output :J1,J0
Full adder K: Input :J1,G1,GROUND Output :Κ2,Κ1
Full adder L: Input :Η1,Ι1,Κ1 Output :L2,L1
Full adder M: Input :I2,L2,K2 Output :M3,M2
Full adder N: Input :H2,M2 Output :N3,N2
Full adder O: Input :M3,N3 Output :O4,O3

The outputs in bold are the final digits of our result. In total that configurations uses 15 1bit full adders. My proposal in post #3 used 26 of them, as it didn't utilize the carry-in pin, as proposed by ErnieM.

P.S Maybe I could have described the circuit in VHDL, but I think it would be even more complex that way.

 

See post #10, last paragraph.

Apologies, I should have read the thread more thoroughly!

 

Yeah me too, I think I didn't get Kermit's idea.