I'm guessing u need to place delay networks in the path of the data signal and clock signal to adjust and get the correct timing for the setup time and hold time? how does a designer get the setup time and hold time for each flip flop or register?

Not quite. All you need is to insure the data signal arrives at a minimum of setup time specification before clock at the IC, and the data signal persists at a minimum of hold time after clock. This can typically be achieved by paying attention to the characteristics of the driving IC and signal propagation time on the board trace. It's rare you have to add delays to the circuit. In rare cases, you can use data and clock trace length ratios to achieve minimum setup and hold times.

 

What is the purpose of the setup and hold times?

To capture a sample of the data signal

What does it accomplish?

To store the data signal

What happens if they are not met?

The Flip flop won't sample or store the data signal

Setup and hold times are properties of the device being used. Signals can be locked in-sync and still violate setup and hold requirements.

True, but the data signals and clock signal need to be "offset between each other in time" so the setup time interval for the data signal is BEFORE the clocks leading edge.

There is an input capacitor inside the Logic Ic chip , flip flop that needs to be charged, so it needs a "setup time" for it to change/rise time so it can sample/store the data signal

The Clock signal just enables turns on the sample/store time

Pretty poor answers that sound more like floundering around than explaining anything.

When you want to store a data bit into a flip-flop, what determines the value that gets stored? Answer in terms of the setup and hold times.