# Logic Gate and TTL question

Discussion in 'Homework Help' started by hitmen, Jan 21, 2009.

1. ### hitmen Thread Starter Active Member

Sep 21, 2008
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I have a question regarding logic gate in "floating" state. This is not in my syllabus. when a logic gate is administered with one input, what happens to the output? Can anyone explain or give me a relevant link?

My second question regard TTL. How do I know what the theortical voltage of a TTL wave is? Is it 4V or 5V? Is there a limit to it?

Jan 18, 2008
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Apr 5, 2008
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4. ### mik3 Senior Member

Feb 4, 2008
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For the TTL family chips if you leave a gate floating then it will be read as high from the chip. If you study the internal circuit schematic of a TTL gate you will see why. However, for CMOS technology this is not true. If you leave an input floating the output will be undefined.
What do you mean by theoretical wave?

5. ### beenthere Retired Moderator

Apr 20, 2004
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I might disagree with the above. A floating input typically rises to the logic tripping point, and becomes a sort of constant noise input, going just high enough to be sensed as a logic high, and then falling just far enough to become sensed as a low. The alternation can occur a a rate into the hundreds of KHz.

With "real" TTL, pulling inputs high through a 4.7 K resistor is good practice, but they can be tied straight to ground. Any CMOS-based logic can be tied to Vcc or ground with no ill effect. Always read spec sheets for the logic family you are working with.

The definition of a "TTL wave" would be nice to have.

If it's like a TTL pulse train, it only has to rise enough to satisfy the input requirement for a logical high state. Each TTL family has a different spec for that.

6. ### italo New Member

Nov 20, 2005
205
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maybe you are asking about try state gate output where the output is floating. TTL logic means tansistor,transistor logic. the input do have a definite treshold of ~1.5v and there is no floating because the output will defenetly consider that as hi. study input loading on these gates as opposed to output loading you will see there is such a thing. CMOS have the input set as hi inpedance treshold so any stray capacitance eventualy will make an open input a real false input. On gates of this kind all pins must be logicaly satsfied to operate properly

7. ### Audioguru Expert

Dec 20, 2007
11,249
1,349
WRONG!
The input low voltage is 0.8V or less.
The input high voltage is 2.0V or more.
Your English and spelling are horrible.

Most TTL outputs never get near 5V when high. Maybe 3.5V if there is no load.

8. ### hitmen Thread Starter Active Member

Sep 21, 2008
159
0
That is my question. How do you know the TTL output? This is because I can only adjust the frequency in my lab equipment and not the voltage!

9. ### beenthere Retired Moderator

Apr 20, 2004
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Logic IC's operate with a fixed voltage. The output may vary voltage-wise with loading and such, but the only concern is that the low goes low enough, and the high goes high enough. It's a 'who cares situation'. If the logic toggles properly, the absolute end point of the states really don't matter.

Proper layout, attention to fan out, and good decoupling techniques are helpful. Read data sheets for more specific information.

As said before, each logic family has its own requirements.

If you want to see something that looks really chaotic, put an oscilloscope probe on a data bus in a computer sometime. Hard to imagine that something that ugly really works.

Apr 5, 2008
19,903
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Hello,

As beenthere told you there are differen levels for different digital famelies.

Greetings,
Bertus

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