jk flip flop reset


Joined Jan 29, 2010
hi mqxp,
Welcome to AAC.
As this is a Homework assignment, please post your attempt at the solution, we can then help you.


Joined Nov 13, 2010
The difficulty with decoding the logic state of a ripple counter is that there can be multiple transient states as clock signals ripple through the flip-flops, possibly generating spurious states in the logic that would need to be suppressed. This can sometimes be easier to deal with if the clock is a short pulse rather than a square wave.


Joined Mar 31, 2012
help, how to make flip flop reset using logic state and use and/or
As already noted, you need to show your best attempt -- doesn't have to work, but we need a starting point.

Also, don't leave ANY input pins unconnected in your circuits (particularly CMOS circuits) unless the device expressly says that doing so is acceptable. Your simulator may not have a problem with it and may do exactly what you expect -- the real world is no where near as accommodating.

As soon as you move away from a simple ripple counter, you should quickly also move away from asynchronous logic -- it is asking for trouble unless you really know what you are doing. So send a common clock signal to all of the clock inputs and then design logic that makes each FF do what you want it to do for each possible set of inputs. This means designing two logic circuits per flip flop, one to drive the J input and one to drive the K input.