Hello,

Attached is the digital circuit of the MC14518B, and its timing diagram. I want to implement the flip flops directly using logic gates since I will then build a VLSI model. The problem is that I'm trying to simulate that circuit and to get the same time diagram as the datasheet says, but it's not been successful. I'm using Proteus but I don't get the same timing diagram. Do you know another more reliable software for this purpose? I also attach the equivalent circuit I'm using for the D Flip Flop. Maybe it's not the sofware but another thing I should take into account.

What are your suggestions?

 

I would think the problem is more likely in your model, then with Proteus.

Show the exact circuit from the simulation screen and the results.

 

I would think the problem is more likely in your model, then with Proteus.

Show the exact circuit from the simulation screen and the results.

I will upload the model. But first, should I use TTL family to simulate the circuit? Or it doesn't matter for simulation purposes?

 

should I use TTL family to simulate the circuit?

Why? The MC14518 isn't a TTL device.

 

I also attach the equivalent circuit I'm using for the D Flip Flop.

Did you modify Clock and Reset so they're LOW and HIGH active, respectively, as they are in the counter schematic?

 

I would think the problem is more likely in your model, then with Proteus.

Show the exact circuit from the simulation screen and the results.

I attach the model that I have in Proteus and the timing diagram, which doesn't look as expected.

 

Does one flip-flop work properly by itself?
When you get one working, then it will be easier to connect them together and get all of them working.

 

I attach the model that I have in Proteus

In the logic diagram, the 3 input gates in the decode logic were 3 input AND with negated inputs. You're using 3 input NAND. The 2 input gate feeding the NOR should also be an AND with negated inputs.

Hint: Use DeMorgan's Theorem.

 

In the logic diagram, the 3 input gates in the decode logic were 3 input AND with negated inputs. You're using 3 input NAND. The 2 input gate feeding the NOR should also be an AND with negated inputs.

Hint: Use DeMorgan's Theorem.

Thank you. That was the problem.