Thanks for help, i understand, can someone explain me is this Moore or Mealy machine, i think it is Moore because on our output only affect Q1(our state, no affect of input).

 

MOD NOTE: Split off from another thread to keep the original thread confined to one topic.

Original thread: https://forum.allaboutcircuits.com/threads/sequencial-counter.132245

 

Thanks for help, i understand, can someone explain me is this Moore or Mealy machine, i think it is Moore because on our output only affect Q1(our state, no affect of input).

It sounds like you have it backwards, but I actually think it is just an English translation issue and that you actually have the correct understanding. So let me rephrase what I think you meant to write.

It is a Moore machine because the output is only affected by the current state and is not affected by the inputs directly.

The test for Mealy vs. Moore is to ask whether, given ONLY the current value of all the memory elements (i.e., the current machine state) are you able to determine the value of ALL of the machine outputs. If the answer is yes to that question under all conditions, then it is a Moore machine. If there is a single instance in which you need to know what any of the current inputs are in order to determine even one of the current outputs, then it is a Mealy machine.

 

Thanks

 

Can you explain me, when we enter results(x,y,D1,D0) from this picture in truth table, it appers that some different combination of inputs(x,y) leads to same present state, if you dont understand me for example, we have state S1(00) and when inputs are 00(x,y)= present state is 00, but in state S1(00) when combination of inputs is 10(x,y)- present state is again 00.
Can you explain me how to implement this situation.

 

Your nomenclature is very confusing. First you use (x,y,D1,Do), but you have given no indication what signals in the schematic are D1 or D0. Then you switch gears and use S1(00). Is this saying that you are in State S1 and xy = 00? If so, which flip flop is equal to what in state S1 (you haven't defined a the mapping between state names and flip flop states).

But this is contradictory to saying that in 10(x,y) that the present state is 00. If the state comes before the parentheses, then the present state in this case is 10. If the 10 is NOT the present state, then what IS it?

Every signal you refer to MUST be annotated on the schematic (or otherwise unambiguously conveyed to the reader). Otherwise you force your audience to guess and engineering is not about guessing.

 

If you see, here D1 is equal Q1*X' + X*Q0( this simbol ' is complement), and D0=X*Q0 + X'Y, and when you take this situation and present them in Karnaugh map, you will see where is D1 and D0 is equal 1(in the map), on the basis of that you can see how our present state will be.
I can take picture of my homework where i did that.

 

 

If you can see in state 00, when X,Y is 00 the next state is 00, and the same next state is when X,Y is 10

 

If you see, here D1 is equal Q1*X' + X*Q0( this simbol ' is complement), and D0=X*Q0 + X'Y, and when you take this situation and present them in Karnaugh map, you will see where is D1 and D0 is equal 1(in the map), on the basis of that you can see how our present state will be.
I can take picture of my homework where i did that.

The point is that there is no way for anyone to "see" any of this because you didn't provide the needed information. Even after you provided the images of your homework where these equations are written, you don't indicate which flip flop provides Q0 and which provides Q1. We have to figure it out based on the equations you provide, which means that we have to assume that your equations are actually correct. But since a big part of the problem in Homework Help is that students often don't set up their initial equations correctly, we are left with no way to verify whether your equations are correct precisely because you forced us to assume that they were correct in order to even guess how to interpret them.

Annotate your schematic!!!

It is NOT that hard to do -- use Paint or any one of numerous free image editing software apps.

 

If you can see in state 00, when X,Y is 00 the next state is 00, and the same next state is when X,Y is 10

I'm unclear as to what you are asking.

Yes, if we are in State X, then it is perfectly legal for us to remain in state X under one or more of the possible input conditions.

Imagine if our machine is reading a number one digit at a time (starting from the most significant) and it's telling us if the number (as it has seen it so far) is divisible by 5. Say that the full number is 34507803. If the number that it has seen so far is 345 then the answer is yes. If the next digit is either a 0 or a 5, then we should remain in this state because the new number, 3450 in this case, is still divisible by five. Similarly, if we are not in this state (which we wouldn't be after we had read 345078) then we should transition back to this state if the next digit we see is either a 0 or a 5.

Draw the state diagram for the schematic you've posted and you should see that there is no difficulty in allowing this behavior.

 

Yes, there are several conditions that remain in the same state, but how to present this sketch.

 

Yes, there are several conditions that remain in the same state, but how to present this sketch.

There are two common ways. The more proper way is to show an arrow that loops from a state back to that same state (called a "self-loop"). The other way is to indicated that transitions not explicitly shown are to be understood as remaining in the same state. This second approach is generally frowned upon unless either the diagram is already so complicated that eliminating the self-loops from it declutters it enough to be worthwhile or if most states stay in the same state for most combinations of inputs. Then having the diagram reflect only those inputs that actually cause a change of state can make things a lot more apparent.

 

But what if that some values we named by dont care condition.

 

But what if that some values we named by dont care condition.

I don't understand. Could you rephrase or perhaps give an example?