As we all know, the mobility of the NMOS device is 3 times greater than that of the PMOS device, so why is it that when we want to tune the switching point of an inverter at vdd/2, we typically modify the W of the PMOS device but not the L of the transistor?

 

Not sure what you are talking about because I cannot see any schematic, but I suspect that switching point will be at or near the current zero crossing, and switching at that time is less stressful to the switching device when done so at a higher current.

 

CMOS chips already use a minimum channel length L. It is impossible to make it smaller. For symmetrical threshold of the gate, the P-channel transistor is made 2 - 2.5 times wider.