I need to build a 2 inverter CMOS using transistors (PMOS and NMOS) from different companies and compare them in the spice. I would like suggestion for what transitor PMOS and NMOS I could use and those would be easy to find .models in the website of the companies. I would use the VDD = 5V.

 

This is Homework Help and not Homework Done For You.

What efforts have you made so far?

Are you modeling inverters that would be made with discrete transistors? Or are you looking for transistor models that would apply to inverters fabricated on an IC?

 

a 2 inverter CMOS

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Do you mean one PMOS transistor and one NMOS transistor, each configured as an inverting stage?

 

This is Homework Help and not Homework Done For You.

What efforts have you made so far?

Are you modeling inverters that would be made with discrete transistors? Or are you looking for transistor models that would apply to inverters fabricated on an IC?

I just asking for suggestion of what PMOS and NMOS transitions you recommend me...About the simulations on the spice and the other problems of my homework I'm doing well. I already tested some transistors (2N7002 e BSS84) from fairchild, but the result wasn't good.

Yess... it's with discrete transistors... I don't have to build the inverter, just make the spice simulations...

Thx

 

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Do you mean one PMOS transistor and one NMOS transistor, each configured as an inverting stage?

Just a simple inverter made with a PMOS and NMOS, like this pic:

 

I already tested some transistors (2N7002 e BSS84) from fairchild, but the result wasn't good.

What was it about the result that wasn't good?

 

What was it about the result that wasn't good?

When I make CMOS Inverter propagation delay there is overshoot in the rise and the fall time. And oscillations during these transitions (rise and fall).

 

What kind of load are you using? What kind of driving circuit are you using?

 

What kind of load are you using? What kind of driving circuit are you using?

I'm using a capacitor with 50pf in Vout. One Vdd = 5V and VPWL source in Vin with:
V1=0 T1= 99.9ns;
V2=5V T2=100ns;
V3=5V T3=200ns and
V4=0 T4=200.1ns

 

Part of your problem is that you are driving the circuit with a completely unrealistic waveform. Your source has zero output impedance, meaning that it can drive infinite current if needed, and you have discrete components that you are driving with an input that is changing at a rate of 50,000 V/us.

For a more realistic simulation, use three inverters in series. Drive the first one with a waveform whose slew rate approximates the output of the second one (though this is not very critical), use the first one to provide a realistic drive signal for the second one, which is your device under test, and use the third one to provide a realistic unit load. You might repeat your simulation using several in parallel for the third one to simulate the desired fanout.

 

Part of your problem is that you are driving the circuit with a completely unrealistic waveform. Your source has zero output impedance, meaning that it can drive infinite current if needed, and you have discrete components that you are driving with an input that is changing at a rate of 50,000 V/us.

For a more realistic simulation, use three inverters in series. Drive the first one with a waveform whose slew rate approximates the output of the second one (though this is not very critical), use the first one to provide a realistic drive signal for the second one, which is your device under test, and use the third one to provide a realistic unit load. You might repeat your simulation using several in parallel for the third one to simulate the desired fanout.

Thanks