Interrupt is a input signal to the processor indicating the event that need immediate attention of the processor.

When interrupt happen processor execute the ISR.

Does the processor react late to interrupt events called Interrupt latency?

 

Interrupt latency is the delay between the activation of the interrupt and the completion of the interrupt service, or at least enough of the service to avoid the loss of information. The minimum value it will take happens when no other event intrudes on the process. It may have a larger value when higher priority interrupts require service before the lower priority interrupts can complete their processing. The actual latency will have a range of values depending on what else is going on.

 

The processor manual will tell you what the latency is, assuming the processor can respond immediately. But there are typically some tasks that have to be completed before any useful work can be done in an interrupt. Some processors will do this automatically, but it may be necessary to store some registers which hold data concerning the process that the processor was working on before the interrupt occurred (and these have to be restored on exit, too). And with 8-bit PIC processors, all interrupts cause a jump to the same location, and the first task has to be a test for which interrupt actually occurred, if the program uses more than one type. So "latency" isn't a completely simple quantity.

 

Not all 8-bit PIC's are single vector. Many of the newer 8-bit PICS have vectored interrupts and some have auto-saved shadow registers to reduce latency and make it more deterministic.
https://microchipdeveloper.com/8bit:vectored-interrupts
https://ww1.microchip.com/downloads/en/AppNotes/90003162A.pdf

//Vectored Interrupts for MVECEN=ON
void __interrupt(irq(IRQ_INT0), base(0x40F0)) INT0_ISR(void)
{
PIR1bits.INT0IF = 0; // Clear INT0 interrupt flag
//place code here
}
void __interrupt(irq(IRQ_ZCD), base(0x40F0)) ZCD_ISR(void)
{
PIR1bits.ZCDIF = 0; // Clear ZCD interrupt flag
 //place code here
}
void __interrupt(irq(IRQ_CMP1), base(0x40F0)) C1_ISR(void)
{
PIR1bits.C1IF = 0; // Clear C1 interrupt flag
//place code here
}
void __interrupt(irq(CLC1_TMR3), base(0x40F0)) CLC1_ISR(void)
{
PIR4bits.CLC1IF = 0; // Clear CLC1 interrupt flag
//place code here
}
void __interrupt(irq(IRQ_TMR0), base(0x40F0)) TMR0_ISR(void)
{
PIR3bits.TMR0IF = 0; // Clear TMR0 interrupt flag
//place code here
}
void __interrupt(irq(IRQ_TMR1), base(0x40F0)) TMR1_ISR(void)
{
PIR4bits.TMR1IF = 0; // Clear TMR1 interrupt flag
//place code here
}
void __interrupt(irq(IRQ_TMR2), base(0x40F0)) TMR2_ISR(void)
{
PIR4bits.TMR2IF = 0; // Clear TMR2 interrupt flag
//place code here
}
void __interrupt(irq(IRQ_TMR3), base(0x40F0)) TMR3_ISR(void)
{
PIR6bits.TMR3IF = 0; // Clear TMR3 interrupt flag
//place code here
}

 

Sorry, I made a sweeping statement there without checking to see if it's really true! But the article that the Microchipdeveloper link goes to says: "Vectored interrupts (available on some of the latest PIC18F devices) improve the response time..." Evidently it's not a common feature, and they're proud to be offering it. Even though the competition has had it for years.

 

Sorry, I made a sweeping statement there without checking to see if it's really true! But the article that the Microchipdeveloper link goes to says: "Vectored interrupts (available on some of the latest PIC18F devices) improve the response time..." Evidently it's not a common feature, and they're proud to be offering it. Even though the competition has had it for years.

It's been around since the k42 series 2017. Proud to say first fabbed in Oregon.
https://forum.allaboutcircuits.com/...rences-that-may-be-missed.143272/post-1212382

A project that used the k42 chip.
https://forum.allaboutcircuits.com/threads/secs-ii-host-using-a-pic18f57k42.157503/