Hey, I am starting to learn about interrupts and how they are executed and I ran into a little bit of confusion based on the reference manual by my textbook which is the same as the one written by Microchip.
Interrupt Latency for One-Cycle Instruction
This is straight from that manual:
"Figure 29-3 shows the sequence of events when a peripheral interrupt is asserted during a one-cycle instruction. The interrupt process takes four instruction cycles. Each cycle is numbered in Figure 29-3 for reference.
(1) The interrupt flag status bit is set during the instruction cycle after the peripheral interrupt occurs.
(2) The current instruction completes during this instruction cycle.
(3) In the second instruction cycle after the interrupt event, the contents of the Program Counter (PC) and Lower-Byte Status (SRL) registers are saved into a temporary buffer register.
(4) The second cycle of the interrupt process is executed as a NOP instruction to maintain consistency with the sequence taken during a two-cycle instruction (see 29.3.2 “Interrupt Latency for Two-Cycle Instructions”).
(5) In the third cycle, the PC is loaded with the vector table address for the interrupt source and the starting address of the ISR is fetched. In the fourth cycle, the PC is loaded with the ISR address. The fourth cycle is executed as a NOP instruction, while the first instruction in the ISR is fetched"
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Which current instruction is last executed INST(PC-2) or INST(PC), that the manual refers to in (2)? Also, what value for the PC is being stored as the return address? PC or PC+2?
I am confused only because in the next section they describe the return process back to main code and the wording becomes tricky. I'm not sure which instruction address they return to. In the diagram it shows that PC = PC but is this the PC or PC+2 from the previous image?
"To return from an interrupt, the program must call the RETFIE instruction.
During the first two cycles of a RETFIE instruction, the contents of the PC and the SRL register are popped from the stack.
The third instruction cycle is used to fetch the instruction addressed by the updated program counter. This cycle executes as a NOP instruction.
On the fourth cycle, program execution resumes at the point where the interrupt occurred."
I feel like they could have been clearer here.
If anyone could help me out that'd be great! Thanks.
Interrupt Latency for One-Cycle Instruction
This is straight from that manual:
"Figure 29-3 shows the sequence of events when a peripheral interrupt is asserted during a one-cycle instruction. The interrupt process takes four instruction cycles. Each cycle is numbered in Figure 29-3 for reference.
(1) The interrupt flag status bit is set during the instruction cycle after the peripheral interrupt occurs.
(2) The current instruction completes during this instruction cycle.
(3) In the second instruction cycle after the interrupt event, the contents of the Program Counter (PC) and Lower-Byte Status (SRL) registers are saved into a temporary buffer register.
(4) The second cycle of the interrupt process is executed as a NOP instruction to maintain consistency with the sequence taken during a two-cycle instruction (see 29.3.2 “Interrupt Latency for Two-Cycle Instructions”).
(5) In the third cycle, the PC is loaded with the vector table address for the interrupt source and the starting address of the ISR is fetched. In the fourth cycle, the PC is loaded with the ISR address. The fourth cycle is executed as a NOP instruction, while the first instruction in the ISR is fetched"
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Which current instruction is last executed INST(PC-2) or INST(PC), that the manual refers to in (2)? Also, what value for the PC is being stored as the return address? PC or PC+2?
I am confused only because in the next section they describe the return process back to main code and the wording becomes tricky. I'm not sure which instruction address they return to. In the diagram it shows that PC = PC but is this the PC or PC+2 from the previous image?
"To return from an interrupt, the program must call the RETFIE instruction.
During the first two cycles of a RETFIE instruction, the contents of the PC and the SRL register are popped from the stack.
The third instruction cycle is used to fetch the instruction addressed by the updated program counter. This cycle executes as a NOP instruction.
On the fourth cycle, program execution resumes at the point where the interrupt occurred."
I feel like they could have been clearer here.
If anyone could help me out that'd be great! Thanks.