Hi all, I've bought a couple of 74LS593 register/counters to make a Program Counter for my breadboard CPU. I'm having trouble interpreting the datasheets for this chip. I've found these sheets:

• SGSTS01966-1.pdf
• 74LS593.pdf

The timing diagram on page 5 of the second sheet is very confusing, especially the register load section. The first sheet has a truth table on page 2 which makes more sense. However, two separate rows say:

1. Data of Q bus is loaded into the counter
2. Data of Q bus is stored in the register

But the logic diagram in both datasheets shows the Q bus values going through the register first before getting to the counter section. So I am suspicious of the comment that the Q bus data can be loaded directly into the counter.

Anyway, what I want is three control lines:

1. Enable the output on the Q-bus, or set it to high impedance (place the PC on the data bus or not)
   
2. Load the register with the Q bus value (load the PC for jump and branch instructions)
   
3. Increment the counter value (increment the PC)

I have a 16-bit PC, so I will need to cascade two '593 counters. Does the following make sense?

• RCO# from the low counter connects to CCKEN# of the high counter as the cascade (# means active low)
  
• The main CPU clock signal is connected to both RCLK and CCLK
• G# is always low. Setting G low means high-impedance output. Setting G high outputs the PC value on the address bus.
• Use CCKEN as the control line to increment the counter value
• Use RCKEN# (active low) as the control line to load the register
• CCLR# is tied high

But I'm still not sure about CLOAD#. I can't work out if I can tie it low, or if I have to associate it (and possibly invert it) with one of the other control lines. I've looked for examples of the '593 in use but I haven't found any. Many thanks in advance for ideas. Once I get my hands on the two chips, i can always prod them with some inputs and see what they do.

Cheers, Warren

 

Looking at the timing diagram on the old TI datasheet, it seems that RCLK goes high to load the register, and then _after_ that CLOAD# goes low
to load the counter.

Perhaps if I OR both RCLK and RCKEN# as CLOAD#? It would normally be high, so no counter load. Assume that RCKEN# goes low on a rising clock pulse, this would load the register. Then on the falling clock pulse, CLOAD# would go low and load the counter.

My design is going to run at a clock speed of < 10kHz, so I'm not worried about timing limitations

And P.S. why did I decide to use the obsolete '593 chip? I'm trying to minimise chip count. Without the '593 I would need two 8-bit register/counters and two tri-state bus drivers.

 

And, stepping back, are there any non-obsolete chips that would suit my purpose? I just stumbled across the 74LS461 which looks even better, but again it is obsolete. Thanks! Warren

 

/CLOAD is used to transfer data from the input register to the counter.

/CLOAD (pin-9) is an active-LOW control signal, i.e. set /CLOAD to LOW to load the counter. Return /CLOAD to HIGH when you want to count.

 

Thanks Mr Chips. So that confirms that the line in the datasheet "Data of Q bus is loaded into the counter" is misleading. When /CLOAD goes low, data from the register (not the Q bus) is loaded into the counter.

Are there any non-obsolete chips that you would recommend that act as a 8-bit register/counter with tri-state output? Even with outputs on separate pins to the inputs?

 

74LS593N is listed as in stock at Digi-Key.

 

Thanks, I'm in Australia and Digikey have some here too!