Interfacing Controller and relay

Thread Starter

Saiteja chinthalapati

Joined Oct 25, 2018
I want to develop a module in which i have to operate 32 relays.
1. Controller ----->Shift Register------>ULN2003------> Relay

but i don't want to use shift register. Can some one suggest me alternate for this. Controller input is DMX-512


Joined Jan 29, 2010
hi S,
As a S/Reg is the obvious choice for operating the relays sequentially, why do you not want to use that solution.??


Joined Apr 4, 2016
Possibly you misunderstand the purpose of the shift register. In this case it is used as a serial to parallel data converter.
The data is shifted out of the controller on one pin (with another used for the clock). A third pin latches the data out AFTER it is shifted into the register. So the relays all change together (or stay unchanged) - the relay state does not shift.

So there is 32 stage shift register but this is followed by a 32-bit latch that actually holds the relay state. This latch is only updated after the new data is shifted into the shift register.


Joined Feb 22, 2014
You could have a look at some latches.. such as the 74HC573, these can allow a faster "parallel" type multiplexer interface for switching.


Joined Mar 10, 2018
This is a solution for the 32 bit SR register with parallel load, parallel out. Single chip.
In fact most of this chips resources un-used, see right hand window which shows re-
sources used/left. Chip is PSOC 5LP. The load comes from 4 - 8 bit registers internal
that you write before you load the internal 32 bit SR shown below from the registers.

The DMX controller solution could possibly be ported from a PSOC 1 design into this
chip as well.

The design routed and built fine. The only thing I am unsure about is the cascade
method as datasheet for the SR component (in PSOC a component is an onchip resource) is
incomplete as it is a community designed component using Verilog. So would have to check SO/SI
operation chip to chip. In any event can be made to work. Or the community component could
be modified as a 32 bit component vs the 8 bit as provided, eg. mod the Verilog code.


IDE, PSOC Creator, and compiler free.

Regards, Dana.
Last edited:


Joined Mar 10, 2018
A user in PSOC can create custom components, either from a schematic or verilog.

This was done using schematic. Inverter just to test it out. Note very few resources used
in the chip, see right hand window.

Again this is a one chip design.


Regards, Dana.


Joined Dec 2, 2017
Just a side thought...

If you are driving 32 relays why not use an 8 channel chip instead of 7, unless you want to use the extra channels?