Inrush Limiter Low side N Channel - Damages

Thread Starter

enggricha

Joined May 17, 2014
74
Hello Everyone,

I have made the attached inrush current limiting circuit for a device powered by a PV panel / SMPS (40V/5A). The dual anode diode is for ORing and reverse polarity protection. Followed by the N-Channel low side Inrush limiter. On the secondary side (V_sys) there is a 8 cell LiFePo4 charger with some large capacitances (>3000uF) for other reasons.

Now the problem is the inrush works only the first time, the next time I power up the inrush does not work and I find that the FET is damaged. I have tried this multiple times and have the same results.

What am I doing wrong here? Pease help.

Regards
Richa
 

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Alec_t

Joined Sep 17, 2013
10,267
the next time I power up the inrush does not work
What is the interval between power-ups? Are you allowing enough time for the charge on the 3000uF caps to decay to zero (or at least below the Vgs threshold voltage)?
 

tindel

Joined Sep 16, 2012
659
It's only limiting the first time because you're blowing up your transistor the first time. Your transistor is turning on so fast compared to the charge of the capacitors, that you may as well not have it in the circuit!

Your transistor turn on is still quite fast. The plateau voltage is ~3V. Your 0-3V Vgs ramp will be ~10ms by my calculations - that's the longest time it will take for your transistor to turn on. If your voltage ramp is linear over that 10ms, and it won't be, your maximum charge current to 40V on your caps will be 12A - meaning your solar array current will limit the current to 5A. An event of 5A > 10ms @ ~20V exceeds the SOA of the transistor.

You have to REALLY slow down your gate charge... by orders of magnitude. Increasing your G-S capacitance to ~1uF or more might get the job done.

Ask me how I know all this! Ha! I have spent significant amounts of time and energy designing precision current limiters for high capacitance loads. It is not trivial.

For more information study how gate charge, plateau voltage, Vgs, Ids, and Vds work together.
[ETA] This App Note is the best I've found on the subject
 
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Thread Starter

enggricha

Joined May 17, 2014
74
What is the interval between power-ups? Are you allowing enough time for the charge on the 3000uF caps to decay to zero (or at least below the Vgs threshold voltage)?
Yes, I am. I will verify this again though. But even assuming that I am not doing this, and assuming the FET is still on the next time I power it. I have FETs that are rated to 50A. Will they still get damaged?

http://www.jjwdz.com/uploadfiles/20181113095941.pdf

FET I am using.
 

Thread Starter

enggricha

Joined May 17, 2014
74
I'll have to study this in more detail to fully grasp what you mean, but I will do a quick test with ~1uF and see if that works.

Can you help explain this part in a couple of lines.

An event of 5A > 10ms @ ~20V exceeds the SOA of the transistor.
 

Picbuster

Joined Dec 2, 2013
982
Hello Everyone,

I have made the attached inrush current limiting circuit for a device powered by a PV panel / SMPS (40V/5A). The dual anode diode is for ORing and reverse polarity protection. Followed by the N-Channel low side Inrush limiter. On the secondary side (V_sys) there is a 8 cell LiFePo4 charger with some large capacitances (>3000uF) for other reasons.

Now the problem is the inrush works only the first time, the next time I power up the inrush does not work and I find that the FET is damaged. I have tried this multiple times and have the same results.

What am I doing wrong here? Pease help.

Regards
Richa
The big cap will keep the system powered up.
a simple way is to disconnect the 10M resistor at the dual diode side.
nest step is to add two small diodes to the 10M this will separate the system working voltage from the 10M.
A resistor to discharge C86 . ( make 10M lower increase C86 and calculate C86's new value)

Remark: it's not common to place an inrush mechanism in the low site as the fet has an internal resistance. Low indeed but it could produce unwanted problems when intermittent (pikes/pulses) or high currents are drawn. (ground plane issue)

Picbuster
 

Thread Starter

enggricha

Joined May 17, 2014
74
The big cap will keep the system powered up.
a simple way is to disconnect the 10M resistor at the dual diode side.
nest step is to add two small diodes to the 10M this will separate the system working voltage from the 10M.
A resistor to discharge C86 . ( make 10M lower increase C86 and calculate C86's new value)

Remark: it's not common to place an inrush mechanism in the low site as the fet has an internal resistance. Low indeed but it could produce unwanted problems when intermittent (pikes/pulses) or high currents are drawn. (ground plane issue)

Picbuster
Picbuster,
Thanks for the recommendations. Can you explain this - "nest step is to add two small diodes to the 10M this will separate the system working voltage from the 10M." The diodes are connected between the 10M and system voltage? I dont follow this.
 

tindel

Joined Sep 16, 2012
659
I'll have to study this in more detail to fully grasp what you mean, but I will do a quick test with ~1uF and see if that works.

Can you help explain this part in a couple of lines.
https://www.onsemi.com/pub/Collateral/NVD5C688NL-D.PDF See figure 11. It is your Safe Operating Area - SOA. Only single pulses less than 10uA can take the full current/voltage. Your single pulse is over 10ms... And you will be traveling from 40-> 0V over that time over your Vds… At 20V (about half) you'll need to keep the current to less than ~800mA. As you can see - a 17A transistor is not truly a 17A transistor!
 

Picbuster

Joined Dec 2, 2013
982
Picbuster,
Thanks for the recommendations. Can you explain this - "nest step is to add two small diodes to the 10M this will separate the system working voltage from the 10M." The diodes are connected between the 10M and system voltage? I dont follow this.
See attached
Picbuster
 

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Thread Starter

enggricha

Joined May 17, 2014
74
https://www.onsemi.com/pub/Collateral/NVD5C688NL-D.PDF See figure 11. It is your Safe Operating Area - SOA. Only single pulses less than 10uA can take the full current/voltage. Your single pulse is over 10ms... And you will be traveling from 40-> 0V over that time over your Vds… At 20V (about half) you'll need to keep the current to less than ~800mA. As you can see - a 17A transistor is not truly a 17A transistor!
I'll study this in more detail ! probably slept through my college lecture that covered this part.

Thanks for pointing this, I wouldn't have stumbled upon this myself.
 

tindel

Joined Sep 16, 2012
659
Thanks for pointing this, I wouldn't have stumbled upon this myself.
You wouldn't have stumbled across something published in the datasheet? I'm confused. Do you not read and understand the datasheet for the parts you use? I typically read a datasheet 3-4 times before I use a part. I need to know that I understand the part before the part ever sees a circuit board.
 
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