I have a rectangular voltage wave of frequency 1 MHz. I need to frequency multiply it to 6 MHz. Is it possible by injection locking?
If any other method for frequency multiplication is possible, please mention.
I thought of creating a PLL, but the control voltage of the PLL has fluctuations in time domain. So the 6 MHz output I would get through the PLL will not have exactly, 166.666ns period throughout!

 

I'm not familiar with injection locking. Perhaps you could provide a reference describing this concept. In a PLL there are tradeoffs you can make in terms of the capture range, the lock range, and the loop time constant. What this means is that you adjust the time behavior of the loop to achieve your desired goal. I would also like to point out that 6 MHz. does not have a period of EXACTLY 166.666 nanoseconds, so I'm not sure what your actual requirement is based upon.

Also I'm not sure what you mean when you say: "So the 6MHz output I would get through the PLL...". The 6 MHz. output comes from the VCO. What drives the VCO is a control voltage derived from a divide by 6 circuit which is then compared to the 1 MHz. reference. How fast the phase comparator is allowed to change the control voltage governs the transient response of the VCO.

 

If you are familiar with the topic of spur generation in PLL, I think it is due to periodic fluctuation of the control voltage of the VCO (whatever might be the reason - be it CP mismatches or divider modulus variation). If I use a PLL to generate 6MHz from 1MHz, then in 1 period of Fref, there will be 6 periods of Fout - meaning that while the control voltage changes through 1 perod of Fref, the 6 periods of Fout will be having different like Fout+df1, Fout+df2, etc. Hence spurs are generated. However I do not want the periods to vary significantly.

You are correct about the period of 6 MHz signal. It is not exactly 166.666ns. I want period to 6 MHz to be with maximum error of 2ps in order achieve spur level in my design to be less than a certain threshold. This is however another topic.

About injection locking I found this on internet-
https://en.wikipedia.org/wiki/Injection_locking

 

If you are familiar with the topic of spur generation in PLL, I think it is due to periodic fluctuation of the control voltage of the VCO (whatever might be the reason - be it CP mismatches or divider modulus variation). If I use a PLL to generate 6MHz from 1MHz, then in 1 period of Fref, there will be 6 periods of Fout - meaning that while the control voltage changes through 1 perod of Fref, the 6 periods of Fout will be having different like Fout+df1, Fout+df2, etc. Hence spurs are generated. However I do not want the periods to vary significantly.

You are correct about the period of 6 MHz signal. It is not exactly 166.666ns. I want period to 6 MHz to be with maximum error of 2ps in order achieve spur level in my design to be less than a certain threshold. This is however another topic.

About injection locking I found this on internet-
https://en.wikipedia.org/wiki/Injection_locking

That would be true of a digital VCO with discrete changes in the VCO output. I was thinking of an analog VCO and a passive loop filter that would trade the speed of transient response against spur generation. You also do not have to use a zero order hold on the output of the phase comparator.

I guess you are saying that you want a 1 MHz. reference signal to drive a 6 MHz. VCO so that the 6 MHz. VCO can control another 6 MHz. VCO. I don't quite see how you get where you want to be with this technique without some form of closed loop control.

 

Yes, I have a 1 MHz signal and want to generate a 6 MHz signal from it. The 1 MHz signal is free from errors. Similarly I want the 6 MHz signal to be error free as well. As I mentioned, I tried with the PLL, but there were errors in phases. BTW I am using a mixed signal PLL - the freq. div. and PFD are digital, the rest are analog.

Also one more thing, can you please elaborate on the following point-
"zero order hold on the output of the phase comparator"

 

Yes, I have a 1 MHz signal and want to generate a 6 MHz signal from it. The 1 MHz signal is free from errors. Similarly I want the 6 MHz signal to be error free as well. As I mentioned, I tried with the PLL, but there were errors in phases. BTW I am using a mixed signal PLL - the freq. div. and PFD are digital, the rest are analog.

Also one more thing, can you please elaborate on the following point-
"zero order hold on the output of the phase comparator"

A typical sampling system will hold the sample value for some period of time until the next sample is ready. This constant value is often referred to as a zero order function. A first order hold would perform a linear interpolation from one sample point to the next. So a sampled phase comparator will produce a sequence of constant values. I guess that given your constraints there is not much I can do for you. Good luck with your research.

https://en.wikipedia.org/wiki/Zero-order_hold