Initial state of 4043 latch outputs

Thread Starter

Dave65

Joined Nov 1, 2015
4
Hi,

I'm powering up a 4043 SR latch with S and R both tied low. The output is always high at power up which feels a bit counter intuitive, given that S has not been given a high.

I understand that the S and R lows would cause the output to latch in whatever state the output was, but why is this high (at power up?)

I suppose my question is, is this expected SR latch (4043 in particular) behaviour? If it is then I'll need to implement something to give R a brief high at power up to force the output low.

Many thanks
 

RamaD

Joined Dec 4, 2009
328
There is nothing mentioned in the data sheet about the output state with both R & S inputs low while powering on. The behaviour could be different for parts from different manufacturers. If any known output state is required on power on, then that must be forced like you had suggested.
 

Alec_t

Joined Sep 17, 2013
14,313
If the latch is consistently in one particular state at power-up, and that state is the opposite of what you want, then just swap the Q and not-Q output connections.
 

dl324

Joined Mar 30, 2015
16,916
If the latch is consistently in one particular state at power-up, and that state is the opposite of what you want, then just swap the Q and not-Q output connections.
A slight problem is that CD4043 don't have complementary outputs:eek:
 

dl324

Joined Mar 30, 2015
16,916
I'm powering up a 4043 SR latch with S and R both tied low. The output is always high at power up which feels a bit counter intuitive, given that S has not been given a high.
If you trace the logic, you'll find that you're seeing the expected state. Below is an annotated schematic of the logic which shows why.
SR-nor.jpg
The only "difficulty" in analyzing latch output is you have to make an assumption. If you guess wrong, you have to walk through the logic again.
 

dl324

Joined Mar 30, 2015
16,916
For completeness, here is the annotated schematic for the CD4044 NAND version:
sr-nand.jpg
That gate would have a LOW output with both inputs tied LOW.
 

Roderick Young

Joined Feb 22, 2015
408
If it's not practical to pulse R high digitally at power up, you could always put a 0.01 uF capacitor between Vdd and the R input, and drive the input through a 1k resistor. That sort of thing is frowned upon in commercial designs, but if this is a hobby project, it should work fine.
 

Thread Starter

Dave65

Joined Nov 1, 2015
4
Just wanted to say many thanks for everyone's replies to what was my first question in this forum :)

I've found it a very useful site/forum and I'm sure I'll be asking further questions in future.

Cheers
Dave
 
Top