Hi,
I'm powering up a 4043 SR latch with S and R both tied low. The output is always high at power up which feels a bit counter intuitive, given that S has not been given a high.
I understand that the S and R lows would cause the output to latch in whatever state the output was, but why is this high (at power up?)
I suppose my question is, is this expected SR latch (4043 in particular) behaviour? If it is then I'll need to implement something to give R a brief high at power up to force the output low.
Many thanks
I'm powering up a 4043 SR latch with S and R both tied low. The output is always high at power up which feels a bit counter intuitive, given that S has not been given a high.
I understand that the S and R lows would cause the output to latch in whatever state the output was, but why is this high (at power up?)
I suppose my question is, is this expected SR latch (4043 in particular) behaviour? If it is then I'll need to implement something to give R a brief high at power up to force the output low.
Many thanks