# increasing frequency of ramp generator

Discussion in 'Analog & Mixed-Signal Design' started by Chandler Timm Doloriel, Apr 6, 2018.

1. ### Chandler Timm Doloriel Thread Starter Member

Apr 5, 2018
33
0
Hello everyone!

In my simulation of ramp generator, I only get small frequency below 100kHz. How should I increase the frequency to 250kHz? I tried changing Io, Ct and Rt but it only results to bad output.

Here are my values that I get a 33kHz triangular output:
Io = 33uA
Ct = 1nF (0.55V)
Rt = 5k
Vdd = 1.2V

In any of these parameters, Io is the most valuable I think? What value should I increase it to result to better output?

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2. ### Papabravo Expert

Feb 24, 2006
12,164
2,673
Apparently the dvices are not capable of operating at higher frequency. Why do you think they will?

3. ### Chandler Timm Doloriel Thread Starter Member

Apr 5, 2018
33
0
What is the maximum frequency this circuit can run? In my reference paper, it ran at 700kHz at vdd= 2. How can I calculate the max frequency it can run?

4. ### Papabravo Expert

Feb 24, 2006
12,164
2,673
It depends on the characteristics of the devices as defined in the simulation.

Mar 10, 2018
3,069
685
Depends on -

1) MN2 Rdson limits speed of discharge of cap.
2) MN2 gate driver speed handling MN2's input C.
3) Speed of hysteresis driver in MN2s gate drive path.
4) Speed MN2 can be turned off.
5) Parasitics associated with ramp cap.

Regards, Dana.

6. ### ebp Well-Known Member

Feb 8, 2018
2,332
811
Look for clues, such as by reducing the capacitance by a factor of 10 and the output current by a factor of two. What would you expect? What does the simulation show?

Showing a sim for a whole bunch of apparently identical cycles just obscures the details. If nothing is shifting with successive cycles, showing 2 or 3 is far better.

7. ### RichardO Late Member

May 4, 2013
2,273
894
If you use LTspice for your simulation others will be able to see better exactly what you are doing. Please post the .asc file if you use LTspice.