Facebook
Google
GitHub
Linkedin
Audioguru again
- Joined Oct 21, 2019
- 6,826
In post #29 he said the detector is a TSOP4838.
Increase IR range
- Thread starter Elecrical_Student
- Start date
Here is the pattern that I found to work with a TSOP4838 when using it for beam break detection.
Format.
start
30 cycles of 38 Khz (789 uS)
Gap of equivalent length to 30 cycles of 38 Khz (789 uS)
Loop 20 times to start
delay about 25 mS
Go back to start
This is the code I used to generate this pattern using an ATtiny13A.
Les.
Format.
start
30 cycles of 38 Khz (789 uS)
Gap of equivalent length to 30 cycles of 38 Khz (789 uS)
Loop 20 times to start
delay about 25 mS
Go back to start
This is the code I used to generate this pattern using an ATtiny13A.
Code:
/*
* _38Khx_beam_V03.asm
*
* Created: 02/03/2022 16:02:42
* Author: Les
*/
; using ATTINY13
;
;Use internal clock at 9.6 Mhz and divide by 1 by setting CKDIV8 fuse bit
;(So Instruction time = 104.17 nS)
;38 Khz is 13.15 uS on and 13.15 uS off. 13.15/0.10417 = 126 instruction cycles
;
;**************************************************************************
.list
;.include <tn13def.inc> ; ATtiny 13
.list
.listmac
;***************************************************************************
;*
;* Global Register Variables
;*
;***************************************************************************
; Note register number is in decimal
.def temp1 = r16 ; Temporary register 1
.def temp2 = r17 ; Temporary register 2
.def count_L = r18 ; Counter low byte
.def count_H = r19 ; Counter high byte
.def count2 = r20
.def cycles_L = r21 ; Counter
.def cycles_H = r22
.def Burst_count = r23
;************************************* MACROS *****************************
;
;
;******************************** INTERRUPT VECTORS ***********************
.CSEG
.ORG $00
rjmp reset
reti
reti
reti
reti
reti ; rjmp timer1_OVF
reti
reti
reti
reti
;
;********************************** TABLES ********************************
;******************************* RESET *************************************
;
; Initialise the stack-pointer
reset:
ldi R16,low(RAMEND)
out SPL,temp1
; ldi R16,high(RAMEND)
; out SPH,temp1
; initialize PORTB
; Bit 0 Input
; Bit 1 Input
; Bit 2 Input
; Bit 3 Output (Pin 2)
; Bit 4 Output (Pin 3)
; Bit 5 Input
ldi R16,0x18 ; Bits 3 and 4 as outputs.
out DDRB,temp1 ;
ldi R16,0x08
out PORTB,temp1 ; PORTB Bit 3 high, bit 4 low
;Set prescaler to value of 1
ldi R16,0x80 ;Set bit 7
out CLKPR,temp1 ;
ldi R16,0x00
out CLKPR,temp1 ;
;Initialize Timer 0
;
; Main program code
;
Main:
;
;
Wave_loop:
ldi count2, 0x14 ; (20 decimal)
cycle30_Burst: ;Send burst for high state
ldi Burst_count,0x1E ; 30 decimal ;Burst lengthe will be 60 * 13.15 uS = 789 uS
Burst_loop: ;Loop is 23 instruction cycles (22 * 0.10417 uS = 2.29 uS) + delays
ldi R16,0x08 ;1 instruction cycle
out PORTB,R16 ; PORTB Bit 3 high, bit 4 low ;1 instruction cycle
rcall Delay_13_15_uS ;3 instruction cycle + delay + 4 for return
ldi R16,0x10 ;1 instruction cycle
out PORTB,R16 ; PORTB Bit 3 low, bit 4 high ;1 instruction cycle
rcall Delay_13_15_uS ;3 instruction cycle + delay + 4 for return
; rjmp Burst_loop ;This instruction is only inserted for testing generated frequency.
dec Burst_count ;1 instruction cycle
tst Burst_count ;1 instruction cycle
brne Burst_loop ;2 instruction cycles for branch, 1 for not branch
NB_delay: ; Delay for 789 uS
; ldi Burst_count,0x3C ; 60 decimal
ldi Burst_count,0x78 ;120 decimal
NB_01:
rcall Delay_13_15_uS
dec Burst_count
tst Burst_count
brne NB_01
dec count2
tst count2
brne cycle30_Burst
rcall Delay_25mS
rjmp Wave_loop ;2 instruction cycle
; --------------------------------------------------
;
;Subroutines.
; *************************************************************************************************************************************************
; * Delay 13.15 uS. This is 126 instruction cycles *
; * Once round the loop is 4 instructions *
; * 126/4 = 31.5 So count 31 loops *
; * So subtract 3 from this gives 28 *
; * *
;Total delay will be (count * 4 * instruction cycle time ) + 1 instruction time. (Instruction time 0.10417 uS * 4 - 0.10417 uS *
; As delay is called twice in waveform loop which includes 22 instruction cycles need to subtract 11 instructions from delay loop to compensate. *
; So subtract 3 from loop count *
; *************************************************************************************************************************************************
Delay_13_15_uS:
ldi count_L,0x1B ;Decimal 28 (Once round the loop is 4 instructions)
D_13_15_Loop:
dec count_L ; Count_L is R18
tst count_L
brne D_13_15_Loop ;If not zero
ret
; ---------------------------------------------
;; *******************************************************************************************************
; * Delay_25mS *
; * 25 mS is 25000 uS instruction time is 0.10417 uS *
; * 25000/0.10417 = 239992 instruction cycles (239992 cycles = 0x3A978 ) *
; * As the loop is 8 instruction cycle long count need to be 239992/8 = 29999 = 0x752F *
; *******************************************************************************************************
Delay_25mS:
ldi count_L,0x2F ;Decimal 29999
ldi count_H,0x75
rjmp D_1mS_Loop1
; *******************************************************************************************************
; * Delay_1mS *
; * 1 mS is 1000 uS instruction time is 0.10417 uS *
; * 1000/0.10417 = 9599.7 instruction cycles (9600 cycles = 0x2580 ) *
; * As the loop is 8 instruction cycle long count need to be 9600/8 = 1200 = 0x04B0 *
; *******************************************************************************************************
Delay_1mS:
ldi count_L,0xB0 ;Decimal 1200
ldi count_H,0x04
D_1mS_Loop1: ;Loop is 8 instructions long
nop ; nop's are so the timing is the same a when it goes through the high byte code
nop
nop
D_1mS_Loop2:
tst count_L ;1 instruction cycle
breq Test_H ;2 instruction cycles for branch, 1 for not branch
dec count_L ; Count_L is R18 ;1 instruction cycle
rjmp D_1mS_Loop1 ;If not zero ;2 instruction cycles
Test_H:
dec count_L ; Count_L is R18 ;1 instruction cycle
tst count_H ;1 instruction cycle
breq D_1mS_E ;If zero ;2 instruction cycles for branch, 1 for not branch
dec count_H ; Count_L is R19 ;1 instruction cycle
rjmp D_1mS_Loop2 ;2 instruction cycles
D_1mS_E:
ret
; -------------End of subroutines --------------
;Les.
