In Minimization of circuits with Logic Gates... K-maps method: is it error in the final result a term to include ONE of More cells (in K-Map) TWICE? like result: yz+wy+x'y+wyz'+w'x'y+w'x'z+wxz 4X4 K-Map (4-variables)

Or NOT an error at all you can have as many overlaps as you like????

 

Depends on what the goal is. If you are trying to "minimize" the circuit, you need to be sure you understand what constitutes "minimal". I'm not being pedantic here as there are many ways of defining what makes one solution more "minimal" than another. Usually the softly-implied criteria is an end result that is in SOP (or perhaps POS) form and that uses the fewest number of groupings in which the groupings are as large as possible. But even that can be ambiguous.

 

SO if not concern strict minimization...
redundant overlap is Not an error, correct?

 

SO if not concern strict minimization...
redundant overlap is Not an error, correct?

Redundant overlap is not an error.
In fact, depending on the application, redundant overlap is desirable. For example, if you are decoding the outputs of a binary counter and looking for a specific binary count, redundant overlap will avoid glitches.

 

Tried to reverse engineer the Karnaugh map. However, one should not even need a K-map to realize that two of the implicants are redundant. So while the logical result is not incorrect, this is a rather poor minimization.