IC breakdown voltage?

Thread Starter

quadhed

Joined Jan 13, 2016
23
Hello. I'm trying to find the value of a cap that will protect an ic from esd.CMOS devices are typical fet technology. Breakdown voltage isn't listed in the ic datasheet which is what I need to calculate the cap. My question is: Should I just use the reverse breakdown voltage of a typical pn junction?
 

Papabravo

Joined Feb 24, 2006
17,296
Hello. I'm trying to find the value of a cap that will protect an ic from esd.CMOS devices are typical fet technology. Breakdown voltage isn't listed in the ic datasheet which is what I need to calculate the cap. My question is: Should I just use the reverse breakdown voltage of a typical pn junction?
The purpose of capacitors has nothing to do with protecting an IC from overvoltage on the power pins. Why on Earth would you entertain this notion? A schematic of what you were thinking about might be helpful. I'm also confused about why you would think that there is a unique value that you could calculate.
 

BobTPH

Joined Jun 5, 2013
4,049
Why do you care whether it is the breakdown voltage as opposed to the voltage at which the chip overheats, or just stops functioning for oither reasons? It is the voltage that you must not exceed.

And how are you planning to use a capacitor to limit the voltage?

Bob
 

Papabravo

Joined Feb 24, 2006
17,296
Caps can suppress voltage spikes, not a constant voltage.

Generally you would use a clamp for ESD not a cap.
Is it not the case that clamp diodes for that purpose are implemented internally on almost every CMOS chip now available with the possible exception 4000 series "A" chips (ca. 1973)?
 

dl324

Joined Mar 30, 2015
13,532
Breakdown voltage isn't listed in the ic datasheet which is what I need to calculate the cap.
This was discussed in another of your threads. I think you're overthinking this issue.

If you don't have unconnected inputs, there isn't much risk of ESD events damaging CMOS IC's in-circuit. This excerpt is from RCA:
1635347656553.png

But don't treat the input protection as being absolute. Manufacturers only test to about 2kV and you can generate static charges many times that.
My question is: Should I just use the reverse breakdown voltage of a typical pn junction?
No. The S/D breakdown voltage will be lower than a typical diode.
 

Thread Starter

quadhed

Joined Jan 13, 2016
23
This was discussed in another of your threads. I think you're overthinking this issue.

If you don't have unconnected inputs, there isn't much risk of ESD events damaging CMOS IC's in-circuit. This excerpt is from RCA:
View attachment 251261

But don't treat the input protection as being absolute. Manufacturers only test to about 2kV and you can generate static charges many times that.
No. The S/D breakdown voltage will be lower than a typical diode.
So, you're saying as long as all unconnected pins are grounded there shouldn't be risk (in circuit) of esd damage? Right?
 

dl324

Joined Mar 30, 2015
13,532
So, you're saying as long as all unconnected pins are grounded there shouldn't be risk (in circuit) of esd damage? Right?
There are no guarantees that someone wouldn't be able to do something to cause damage by ESD.

If your objective is to make it foolproof, it has been said that fools are pretty ingenious when it comes to doing dumb things.
 

MisterBill2

Joined Jan 23, 2018
9,838
Protecting inputs is done best with external clamp diodes, as the internal diodes may not have enough current handling ability. Of course some current limiting resistance is also needed, and a noise capacitor is often recommended.
I am not aware of ever needing spike protection on IC power pins, as most assemblies use a stable power source.
 
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