When does the (actual) clock synchronization in multimaster I2C bus take place? Is it always before arbitration?
It looks like sometimes clock stretching is called synchronization, but I got the impression from the I2C specs that clock stretching is just "adding wait states" by a slave, whereas the clock synchronization is done only between masters (the slaves don't generate clocks).

The I2C spec says:
"However, if another clock is still within its LOW period, the LOW to HIGH
transition of this clock may not change the state of the SCL line. The SCL line is therefore
held LOW by the master with the longest LOW period."

Also this suggests that the synchronization is only participated by the masters also participating the arbitration: "When all masters concerned have counted off their LOW period,..."

 

Found it.
An older spec from Philips said:
"8.3 Use of the clock synchronizing mechanism as a handshake

In addition to being used during the arbitration procedure,
the clock synchronization mechanism can be used to
enable receivers to cope with fast data transfers, on either
a byte level or a bit level."

And the current spec also says (about clock stretching):
"Slaves can then hold the SCL line LOW after reception and acknowledgment of a byte to force the
master into a wait state until the slave is ready for the next byte transfer in a type of
handshake procedure."

and

"On the bit level, a device such as a microcontroller with or without limited hardware for the
I2C-bus, can slow down the bus clock by extending each clock LOW period. The speed of
any master is adapted to the internal operating rate of this device."

So clock synchronization seems to take place during arbitration, but also when bit level clock stretching is used.