Hello:
i use MTK7628 with NxP7001 through I2C communication line, and get below strange waveform, anybody know why after master release the SDA line and before the slave pull the line low (ACK), there is a drop on the high level signal? my power supply for those 2 IC is 3.3V, and pullup resistor on the line is 4.7K.


Thanks and regards

 

The transmitter is releasing the SDA line in preparation for the receipt of the ACK pulse.

 

The oscillograph seems to show just some portion of a larger transaction as there are no start or stop signals sent.

There is also a glitch after the 9th clock pulse on the data line.

Also note that the high level drops just before the ack, and after the ack and the glitch the data level remains at this lower level.

I would want to see more data before coming to any conclusions, especially links to the devices you use:Google did not find them.

What is the master? Is it hardware or software? If your master is actively driving the data line there could be a contention when the slave is trying to pull it low.

 

The oscillograph seems to show just some portion of a larger transaction as there are no start or stop signals sent.

There is also a glitch after the 9th clock pulse on the data line.

Also note that the high level drops just before the ack, and after the ack and the glitch the data level remains at this lower level.

I would want to see more data before coming to any conclusions, especially links to the devices you use:Google did not find them.

What is the master? Is it hardware or software? If your master is actively driving the data line there could be a contention when the slave is trying to pull it low.

The transmitter is releasing the SDA line in preparation for the receipt of the ACK pulse.

The transmitter is releasing the SDA line in preparation for the receipt of the ACK pulse.

 

Hello Papbravo:
thank you very much for the reply.
but may i know why after the master release the data line, the high level voltage will be dropped a bit? sorry i am new to the I2C, for my understanding both the master and slave should be open drain circuit, the line is pulled up by outside pullup resistor, the master/slave can pulldown the line when they need, but once they are not doing so, the line should just back to the pullup voltage, am i right? but in my circuit, seems as long as the line is controlled by slave, the high level voltage will be dropped a bit such as during the slave send back the acknowlege as well as during the slave sending back data...
by the way, as a hardware engineer, i also want to know what kind of hardware circuits inside the micro-controller for the SCL/SDA pins if the datasheet claim the I2C function is done by hardware?

Thanks and regards

 

Since you have not shared the schematic of your setup we can only speculate about what might be going on. My guess is that you have two chips with slightly different Vcc levels that are driving the SDA line rather than relying on the one or more passive pullups. An active driver is used in many cases to allow faster bit rates by not having to allow for the slow risetime of a passive pullup.

Links to your datasheets would also be helpful. I'm not fond of going to websites that I cannot read.

 

Hi, ErnieM:
Thank you for the feedback.
Yes, you are right, the waveform i post is just part of data. and there is a gitch after the 9th clock pulse line,don't know
why...and our problem is the I2C sometime is not work well.the I2C function is controlled by hardware inside the micro-controller,
may i know what do you mean by "If your master is actively driving the data line"? what should i check if the I2C controlled
by micro-contoller hardware?

Thanks and Regards

 

Since you have not shared the schematic of your setup we can only speculate about what might be going on. My guess is that you have two chips with slightly different Vcc levels that are driving the SDA line rather than relying on the one or more passive pullups. An active driver is used in many cases to allow faster bit rates by not having to allow for the slow risetime of a passive pullup.

Links to your datasheets would also be helpful. I'm not fond of going to websites that I cannot read.

Hi, Papabravo:
thank you for you quick reply.
i know for master, it indicate the line is open drain, for the slaver, it seems weakly pullup, i need to check again. may i know what is "active driver"? it done by hardware or software?

thanks and regards

 

What you could do is add a pull-down resistor of about 4x the value of your pull-up. Then when the line isn't being driven by either unit, you should definitely see a drop in voltage, to about 4V if Vcc is 5V. If that doesn't happen, then one or other unit must be actively driving the line.

 

An active driver is hardware that can both source current and sink current. So if the master is open drain, then when it releases SDA, the pullup and the slave device are fighting each other resulting in a small drop prior to SDA being pulled low for the ACLK pulse.

 

Thank you Papabravo.