Dear Team,

Question 1:

Below is the I2C wave from captured .You can see that the ACK is coming to 0.8V.May I know is this due to the presence of level shifter.

Please see my circuit below.The pull up used is 10K,LOW side voltage is 2.9V and HIGH side voltage is 5V.



Qusetion2:

You can see that two acknowledgements are coming (Yellow Circle).

After that you can see that there is no ACK and SDA pulled to LOW and SCL pulled to high.

No clock is coming after that.May I know is it an expected behaviour.I mean clock properly comes from Arduino only when it receives ACK properly.

Question 3:

Looking closely at trace(1st image), it appears that SDA is transitioning low-to-high while SCL is low. This appears to be the controller sending the STOP condition, in the middle of a frame.
Is this a firmware issue

 

I'm not familiar with a PCA9306 so maybe it's not needed, but you are not showing any pullups on either SCL. That could explain the transition you are getting mid clock... one device is releasing the line before the other takes over.

Edit... I checked the datasheet and on the "normal setup" schematic it does indeed show pullups on SCL

 

I'm not familiar with a PCA9306 so maybe it's not needed, but you are not showing any pullups on either SCL. That could explain the transition you are getting mid clock... one device is releasing the line before the other takes over.

Edit... I checked the datasheet and on the "normal setup" schematic it does indeed show pullups on SCL

The clock to the DUT is not directly given from Arduino.We are using a circuit called voltage modulator.This modulator is designed using a SPDT switch.One I/P of the switch is connected to 3.8V and another I/P is connected to 2.9V.The clock coming from Arduino is used as a control signal for this SPDT switch.If CLK is high output will be 3.8V and when it is low the output will be 2.9V.

This 2.9V and 3.8V is coming from a Power analyzer(Key sight N6705C).The 2.9V is also connected to VREF_LOW of the level shifter. The modulator circuit is given below.

 

@hoyyoth Nevermind... I was at the tail end of my lunch break and thought I would check out what was on here and thought I could be of some help. I had to be quick and get back to work

After looking at your schematic again I realized I missed a few things. This sounded like a similar problem I had with a TCA9543 at one time with a missing pull up.

As far as the transitions on the low clock pulse... I have seen this sort of thing when the slave releases control of the data line after an ACK. It doesn't mean anything as the master is not looking for it, and the slave should recognize it. Normally the master would pull the data low again immediately after the ack clock cycle and then start the stop sequence.

Personally there are too many unknowns in your circuit for me to wrap my head around. Every time I have encountered a similar problem it has been circuit related.

Good luck

 

Edited because I realized I totally screwed up....

figure out why you are not getting a 0V ACK first and the rest may just fall into place.