The simulation shows that there is a huge input current spike it LT's example design. I noticed the same thing in my design and wanted to check theirs to see if it was something I was doing. Why is this happening? In the plot I measured the current through Cinb1 in the red which went up to almost 440A. Then the current through Cinc1 is nearly 25A. The caps would not be able to handle this, is this something that can be ignored since LTspice will not always represent what happens in the real world? I notice if I reduce the input capacitance the spike becomes much less, but of course I do not want a lot of ripple at the input.