Hi, I am familiar with using dual port Block RAMs in Xilinx FPGAs. We usually generate the Block RAM IP Core in Xilinx Vivado and configure their ports, size and memory width etc. Then we instantiate the digital design to perform read/write operations between the digital design and the Block RAMs.

How do we work with DSP slices ? and do we also need to intentionally add in our design ? Do we also configure each DSP slice we need to add in our design and in what application we need to use DSP slices ?

 

In general, not a FPGA or DSP expert.
DSP 'slices' are commonly used for Multiply–accumulate operations in things like FIR filters.
https://skills.microchip.com/dsp-features-of-the-microchip-dspic-dsc/694376
https://onlinedocs.microchip.com/ox...UID-808783F7-D5E4-48F8-B95D-C40128A450E8.html
https://www.allaboutcircuits.com/ip-cores/arithmetic-core/multiply-accumulate/
https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR.html

Applications:

 

I know basic some DSP stuff from a graduate level course. There are mainly two types of digital filters. FIR and IIR.

The FIR filter is always stable as there is no pole in the transfer function of impulse response. The output of the FIR filer can be found/solved using convolution that only works for linear and time invariant systems.

The IIR on the other hand has a feedback from output to input and that is the reason IIR filters have poles and can be unstable. The IIR filter can be stable or un-stable because of presence of poles in the transfer function of impulse response of IIR. If the location of all poles and zeros located inside the unit circle of z-transform the IIR filter is stable. If located outside the unit circle then un-stable.

How do DSP slices in the FPGA help in the implementation of digital filters ? I guess DSP slices are multipliers that are successive additions to implement multiplications. Is that true that using DSP we can implement the multipliers in efficient way ?

 

hi engr,
I Googled
How do DSP slices in the FPGA help in the implementation of digital filters
Many hits.
E.

 

I found answers to following questions.

What is DSP slice ?
"DSP Slice consists of 25 bit by 18 bit two's complement multiplier followed by three 48 bit three path multiplexers. This is followed by three input adder/subtract or two input logic unit."

What is DSP slice in FPGA ?
"Many FPGA boards have specific multiply-accumulate hardware accelerators, called DSP slices that speed up the execution of signal processing functions. DSP slices vary in size depending on the vendor."

 

Check the DSP book by Xilinx (targeted for Virtex series) online.