Hi,

I am studying signal processing. On this matter, there exists signals at 10kH (audio signals), but there exists signals on the 1GHz frequency. Suppose I want to acquire and process this high frequency band signals (1GHz signals). Suppose also I have an analogical to digital converter (ADC) operating at this 1GHz rate (i.e. the ADC is a 1 giga samples per second). I will need a microprocessor in order to digital processing the samples signal, and so my doubt occur at this point: there is not available at the market a >1GHz clock micrcontroller or FPGA.

So, althougth it is possible to have a 1GSPS ADC, how could I buffer to the memory these sampled data at the same ADC frequency, in order to have a set of data sampled at 1GHz?

In other words, is it possible and is it the best practice, to have an ADC synchronously connected to a kind of memory (it could not be a DDR memory since DDR is 333MHz) both and so sampling and on-line storing in the memory data at 1GHz?

Hope I could be clear explaining my doubt.

Thank you!

Nathan.

 

One possible answer is to have 16 separate ADC/Memory subsystems. Each one doing a sample every 8 nanoseconds. That is two samples every nanosecond which is what Shannon's theorem demands for sampling a 1GHz. signal. To process the signals, you just access the memory subsystems in the proper order.

Another possible answer is to down convert the signal to a more manageable range. In the process you extract the modulation and discard the carrier. Then sample the lower frequency signal.

 

the ADC is a 1 giga samples per second)

For an 8-bit converter that would require storage of 1 gbyte/s or 1 Tbyte for every 16.6 seconds of data.
I don't think that is what you want to do.

 

If you intentionally undersample, you are essentially "down-converting", by sampling in a higher Nyquist zone, 3rd zone for example.

Why oversample when undersampling can do the job?

 

Hi,

For an 8-bit converter that would require storage of 1 gbyte/s or 1 Tbyte for every 16.6 seconds of data.
I don't think that is what you want to do.

I agree with your opinion in the sense that it is an uncommon transfer rate of course. Nevertheless, I think DDR3 actually may be adequate to store these amount of data at this frequency. Am I mistaking? If you could please take a look at this reference:

https://pt.wikipedia.org/wiki/DDR3_SDRAM

One possible answer is to have 16 separate ADC/Memory subsystems. Each one doing a sample every 8 nanoseconds. That is two samples every nanosecond which is what Shannon's theorem demands for sampling a 1GHz. signal. To process the signals, you just access the memory subsystems in the proper order.

I hope this kind of solution could work. It have a lot of advantages. Do you have noticed about anyone who implemented something like this?

If you intentionally undersample, you are essentially "down-converting", by sampling in a higher Nyquist zone, 3rd zone for example.

Why oversample when undersampling can do the job?

Ok, reading!



Bye.

 

Hello,

When posing links to the wiki, please use the english version of the page:
https://en.wikipedia.org/wiki/DDR3_SDRAM

For dynamic ram, you will need a controller, that does the refresh of the ram.

Bertus

 

Hello,

When posing links to the wiki, please use the english version of the page:
https://en.wikipedia.org/wiki/DDR3_SDRAM

For dynamic ram, you will need a controller, that does the refresh of the ram.

Bertus

I'm sorry for the mistake on the correct language, I did not payed attention to the Portuguese refference since I am in an english language forum. I am trying to fix it, but it is appearing an alert that the content is SPAM?! (picture bellow)

Thanks for replying.

 

Hello,

I already posted the english page.

Bertus