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How to design flip flops counter up 0-13
- Thread starter domol
- Start date
Synchronous RS Flip-Flop. please hlp me
Is this homework?
yes
For homework, you need to show your work and members will try to guide you to a solution.
Post your truth/excitation table, Kmaps, and equations.
Petkan:
The general approach is to take a counter of say up to 16 (like 74HC93), decode 13 and feed it to its clear.
13 dec is 1101 binary i.e. has 3 ones, which is more than the 2 input clear. Additional gate is required.
A more flexible approach is to use a programmable reversive counter such as 74HC193. You can use it in forward or reverse.
Let us start with reverse. Use the Borrow output to drive the LOAD input. Define the parallel load 4 bit word as 12 dec (1101b).
Apply the clock to the reverse clock input. The counter will count down and after reaching 0 will generate a borrow on the next clock.
This borrow will pre-load 13 again and the process will repeat itself. Same could be done in forward by pre-loading the complement of 13 to i.e. 3. Note that normally the borrow (or carry) tracks the clock low state duration. When used to drive the Load - borrow will terminate prematurely as the counter state will change from 0 to 13 within the same clock. This is a risk of very short pulse and racing condition. If you encounter problems you may add delay to the borrow output (an RC or two inverters)
Probably not when the homework assignment is to design it using flip flops.
Even were that not the case and using a counter IC is fair game, you are NOT supposed to just hand over the solution to a homework problem on a silver platter.
But even if that weren't an issue, your solution is not synchronous. In fact, you yourself point out some of the traps that you open yourself up to by using asynchronous logic.
It has been stated that the problem is to design a synchronous counter with RS flip flops.
