How to desgin the (pull-up or pull-down) resistor on a two CPUs system?

Thread Starter


Joined Jul 15, 2020
Hi all,
I study a two CPU system. There is some control signals from CPU -> CPLD -> BMC (AST2500). The input voltage of both CPU to CPLD and CPLD to BMC is 3.3V and the same signal (secure boot authentication), but the pull-up resistor is 4.7K from CPU to CPLD, and the pull-up resistor is 10K from CPLD to BMC. Furthermore, one resistor is pull-down at CPU1 and another is still pull-up at CPU0.

The questions:
1. How to design the resistor and pull-up or pull-down?
2. Should active LOW be used with a pull-up resistor? is this related to the internal resistor of ICs?

For example:
1. From CPU to CPLD, the net S0_SCP_AUTH_FAILURE_L and S1_SCP_AUTH_FAILURE_L are with pull-up 4.7K (active LOW).1594807520222.png 1594807551817.png

2. From CPLD to BMC, the net S0_BMC_GPIOJ2_SCP_AUTH_FAILURE_L is pull-up 10K, and S1_BMC_GPIOZ5_SCP_AUTH_FAILURE_L is pull-down 10K.
Why is the same function with different resistors and pull-types? It might be open-drain, so it's ok with pull-up or pull-down? Just keep any state?


Joined Jan 30, 2016
If youre connecting an output to an input you don't need, nor should you have, a pullup or pulldown unless:

1/ The output is open-collector/open-drain. Then you need a pullup. 10k to Vcc of the input device would generally be acceptable, unless this is a multidrop scheme i.e. I2C when a specified pull-up (1k8 for I2C) should be used, or other value based o rise-time requirements.

2/ The output can be tristate. Then you need a pullup or pulldown to set the desired input state (High or Low). If its a bus with multple i/o there are some special considerations on loading and capacitance to be considered.

3/ The devices are connected via a connector. Then inputs should be pulled up or down (convention is up) for input protection. Other protection against ESD may be needed/wanted.