In order to implement OR4 logic in 45nm process to drive a 10fF on-chip capacitance, we end up with two options, (A) NOR4+INV; (B) 2 NOR2 + NAND2, shown as Figure 3(A),(B) below. Assuming sizes of all the logic gates are tuned to follow the inverter with 2:1 P/N ratio and per unit width gate capacitance Cperwidth=1.5fF/um.

 

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i have try to solve it but i didn't get the result if you can help me. solve it for me

 

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