How to calculate the size of NAND2 gate ?

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Irfan Tariq

Joined Dec 28, 2018
2
In order to implement OR4 logic in 45nm process to drive a 10fF on-chip capacitance, we end up with two options, (A) NOR4+INV; (B) 2 NOR2 + NAND2, shown as Figure 3(A),(B) below. Assuming sizes of all the logic gates are tuned to follow the inverter with 2:1 P/N ratio and per unit width gate capacitance Cperwidth=1.5fF/um.
 

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JoeJester

Joined Apr 26, 2005
4,390
The rule in the homework area is to show your work so people can see where you went astray. Anyone showing you will not help you. Knowing where you were in error by answering the questions posed by the members here will be more of a benefit to you than giving you the answer.
 
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