I tried looking for some general guidelines on this by searching the forum, but didn't have much luck, so I thought I post the question.

I realize the question as phrased is way too general, but let me add some specifics. (I ask the more general question because I'd like to better understand how to evaluate this more generally, not just for this example.)

Suppose I want to build a chasing LED circuit with a 555 and 4017, but I don't just want 10 LEDs, I want 2,000 LEDs! (I am not really doing this, just using it as a specific example to gain an understanding of my question.)

So for this, I need some 220 4017 ICs, and each of them needs to receive the clock signal generated by my 555. (I realize that the signal goes through an AND gate and does not go directly to the 4017.)

The 555 is powered by a wall transformer and a 5V voltage regulator. (I am using this example because I would imagine that the V matters for the answer.) The 4017s and LED are powered separately (just to simplify the question and example).

So my question is: how many 4017s can I run from the 555s clock signal?

(Whatever the answer may be, would using buffer gates -- say a 4050 -- to propagate the signal to x number of 4017 be a good solution?)

Thanks for any help in understanding this.

Luke

 

The NE555 is not a great choice for driving CMOS, but ignoring that detail for the same of discussion, there are a few things to consider here.

As you add CD4017's at some point you will have so much capacitive loading on the output of the NE555 that the output will have rise and fall times too slow to meet the maximum rise and fall time specifications for the CD4017's.

As you add CD4017's at some point you will burden the output of the NE555 with so much current to charge and discharge the capacitance of the inputs of the CD4017's that you exceed either the maximum peak output current specification for the chip of the chip overheats.

As you add CD4017's at some point you will burden the output of the NE555 with so leakage input current from the CD4017 that you exceed either the maximum peak output current specification for the chip of the chip overheats.<= This is mainly a problem with B series CMOS and is unlikely to the a limiting factor unless there are many CD4017's and the clock speed is very low.

At high clock speeds you might have to worry about the pulse duty cycle changing because the output sink and source currents of the NE555 are not the same.

If you were clocking data into a register you would need to worry about timing: data setup and hold timing in particular, and in that case you would have to worry about how the loading on the driver's output affects rise and fall times so that you can predict delay in clock or enable edges.

You can use buffers to generate more copies of the clock signal while having less of an affect on timing and waveform. In the case of an NE555 a buffer would restore the signal to the rail-to-rail swing with which CMOS works best.

That is probably not an exhaustive list but it is what comes to mind first.

 

(Let me add another variable that I'm curious about. For my example, setting up 2,000 LEDs is going to require some space, so the clock signal will need to travel a certain distance. Let's posit that the size of the project will be about 12 feet, with the 4017 ICs distributed somewhat evenly along that length. Is this a factor to be considered for the question above?)

 

Delay caused by interconnects won't be significant in your proposed circuit.

 

To what use will you put the LEDs? If it is for a visual display the extra 15 to 20 nanoseconds won't be observedd=.

Is this something you are thinking about actually building?

 

(Let me add another variable that I'm curious about. For my example, setting up 2,000 LEDs is going to require some space, so the clock signal will need to travel a certain distance. Let's posit that the size of the project will be about 12 feet, with the 4017 ICs distributed somewhat evenly along that length. Is this a factor to be considered for the question above?)

The general issue you are referring to here is known as "clock skew" and it matters in high speed designs or designs in which the arrival of signals relative to the arrival of clocks is important. For the example you've based the discussion on, it shouldn't matter at all. For designs where it does matter, the use of a "clock tree" is often the solution and its design can become quite involved.

 

"Is this something you are thinking about actually building?"

Not exactly. I was just trying to learn more about this issue in general and just tried to come up with a fairly simple and clean example.

I was thinking of building something similar, but with 288 LEDs. It would be a clock with LED that light up sequentially as the day goes on (288 LEDs: one for every 5 minutes of the day). The idea would be that whatever time segment we were in would have a flashing LED, while all the LEDs behind it would be steadily lit. I built a 4 LED prototype that does this with flip-flops, and some AND and OR gates. It works nicely. I'm not sure if I'll really build an actual clock version, but it did get me curious about the clock signal propagation issue. (If I did build it, I would get the clock signal from dividing the AC, not an NE555.)

But really, I built the little 4 LED version as a learning exercise, and thinking about what problems might come up if I scaled it up prompted me to want to learn more about this.

Thanks

 

Traditionally, one would determine gate fan-out by analyzing manufacturer's data specs on input and output currents and input threshold voltages. Fan-out of 10 max for TTL gates is generally recommended.

CMOS gates have very low input currents. Output drive exceed input currents by a factor of 10,000. As others have pointed out, signal integrity will suffer at higher clock frequencies since the input capacitance is of the order of 5pF. Multiply this by the number of inputs and the capacitance quickly adds up.

Besides that, you will have to be concerned with false triggering as the signal quality degrades over long wire lengths.
Splitting the clock into multiple clocks using buffer/drivers would be the desired option.

 

I will recommend to use 10 pnp 2SA684 to drive the CD4017:
NE555 → 1n4148 x2 → R → Base of 2SA684 → C of A684 x10 → CD4017 x220

 

Cascading 4017's you get 8 outputs per IC, might consider 74HC154, 4 line to 16, active low.
Something like 20 ea. 74HC154, 4 bit counter & clock. Add 2 diodes for each output to inject
modulation for off LED ? With all LEDs on, will need an R for each output.
I'll throw in an outline with just one circulating LED; easily converted to all on.

 

10 posts and I still don't see something that is sorta kinda maybe important: What is the clock frequency?

If it is something like 1-10 Hz, you'll never see the skew from one end of the string to the other.

If you increase the system voltage to 6-9 V or more, a standard or CMOS 555 will drive the string with no problem. The rise and fall times of a 4017 are specified as "unlimited" when using pin 14 as the clock input because that pin has a Schmitt trigger input stage. This is a two-edged sword: The Schmitt circuit cleans up slow edges, but it als changes the threshold voltages for state changes. The input requires the clock low voltage to be less than 33% of Vdd, so it is best to keep it below 25% for margin. Same for the input high voltage - 67% required, 75% for margin. The higher the system power voltage, the more room there is between a 555's output voltage range and the 4017's input voltage range.

ak

 

Fast clock- 288 PPD.
Inserting modulation into traveling blank
If 5 mm LEDs, that is about a 33 cm radius, lots of room for 1/16 in. self adhesive copper tape buss lines ?

 

Looks like I missed post # 7. I think that you will need some OR's when stacking LEDs using 4017's.
Not sure on how to modulate leading LED.

 

Not pretty, but I think it can be done.
For blinking LED we use a string of 18 decoders, 74HC154, active low. ( post # 10 ) & modulate the output by putting a square wave on G2 which makes all stages high for 1/2 cycle. trailing LEDs, from 36 shift registers, 74HC164, by loading highs. Both strings have same clock. The result should be as in post # 7.