Hi All,

As i recently came to know that the energy is not travelled in the wire infect it is travelled in the space around the wire in the electrical and magnetic field so my question is particularly related to the IC fabrication. In IC fabrication we have micro-scale deployment of transistors and wire connections. On a single dice which is smaller than the palm has millions of transistors, so it means that the these connections and transistors have very close space to each other so at such small scale if the energy is delivered in space then it means that this energy must have interfered with the other metal connections energy so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?

The electric field between different wires in the IC does interfere with the other wires. If you are familiar with capacitors, and the concept of capacitance, it is not hard to imagine these different wires acting as plates on a capacitor.

The electric field links different wires together capacitively which causes undesired effects such as cross-talk (where a signal from one wire will pass to a neighboring wire through this capacitive link); and increasing rise/fall time of the signals, due to the the all-important RC time constant, which is a major factor limiting clock rates in ICs since the circuit must be able to rise and fall within one clock cycle (the clock itself, for example) are a major consideration in IC design.

Some methods to reduce this capacitance can involve using a different substrate material with a smaller dielectric constant (un-realistic due to maturity of current IC technologies, and buttload of cash required to change these processes), or more realistically, changing the dimensions of the traces by separating them as far as possible from other traces, making them as short as possible, and making them as narrow as possible (within reason, because narrower traces will also increase resistance and therefore the time constant)

If you would like to learn more from someone more competent at explaining this than myself, check out This Article from Cadence.

 

Welcome to AAC!

changing the dimensions of the traces by separating them as far as possible from other traces

Another option is inserting a metal line between the signal wires. Even if the wire between the critical signals is floating, it helps. But connected to power or ground is better.

 

Welcome to AAC!
Another option is inserting a metal line between the signal wires. Even if the wire between the critical signals is floating, it helps. But connected to power or ground is better.

At the IC fabrication level @dl324
I've not seen extra wires inserted

As for a floating wire, I'd say on a PCB, it would actually make things worse as that just makes a capacitively coupled antenna.

 

At the IC fabrication level @dl324
I've not seen extra wires inserted

It was one of our design BKMs (Best Known Methods). Spacing lines apart could cause problems with minimum metal density requirements.

As for a floating wire, I'd say on a PCB, it would actually make things worse as that just makes a capacitively coupled antenna.

You have two capacitors in series, so the coupling between signals is reduced. It's better to have the intervening wire connected to a supply but, for cases where that's not possible, floating wires are better than nothing. Of course, you don't have minimum metal density requirements on PCBs, so you could just increase space between wires.

 

It was one of our design BKMs (Best Known Methods). Spacing lines apart could cause problems with minimum metal density requirements.
You have two capacitors in series, so the coupling between signals is reduced. It's better to have the intervening wire connected to a supply but, for cases where that's not possible, floating wires are better than nothing. Of course, you don't have minimum metal density requirements on PCBs, so you could just increase space between wires.

Have a good Christmas @dl324
Well just disagree,

 

Isn’t there a path created to the substrate?

paths to the substrate exist through parasitics on all chips. but due to size, capacitive issues are generally more of an issue than inductive/transformer effects.

Here, read these 2 articles I wrote for Electronic Design a while back:

“Noise Reduction Is Crucial to Mixed-Signal Design Success Part 2”
Electronic Design Magazine, 12/4/2000

“Noise Reduction Is Crucial to Mixed-Signal Design Success Part 1”
Electronic Design Magazine, 10/30/2000

(yikes! over 20 years ago!) These are old, but they deal with coupling issues of noise within a chip. Pretty basic look at the topic.

- Jerry