I'm building an 8-bit SAR analog to digital converter. I'm having trouble with the simple op-amp. The ADC has to be able to take up to 100kHz. The input signal is a 620mV P-P sine wave with an offset of 1.2V. This is the voltage swing of a thermistor that I'm going to use for the input when it's finished. At 100kHz the output signal looks clean with no noise. When I decrease the frequency down from 100kHz the noise will start to show up at the bottom of the sine wave at around 20kHz and increases as the frequency goes down. The source voltage is 5 volts. For the N-channel MOSFET's I'm using ALD212900's and for the P-channel MOSFET I'm using ALD1117. I can't figure out how to get rid of the noise shown in the pictures. I've tested all the gates for ringing and didn't find anything.

 

Have you tried using a commercially available op-amp?

 

Where are the p-channel MOSFETS? What is the frequency of the noise? Is it 50/60 Hz? Maybe your op-amp is unstable at low freqs. Did you bother to simulate the circuit? What does your circuit look like? Where are your by-passing caps?

 

Would you please put your scope in FFT mode and see what frequencies show up. It might be that the amplifier is going into oscillation. It might be going into oscillation at a certain DC level and it may take time for the oscillation to build up to a noticeable level, so running with a high frequency signal, the oscillation either doesn't happen or is too small for you to notice on the scope.

The solution might be to decrease the loop gain or roll off the feedback, depending upon your circuit.

A quick check in FFT mode should tell you a lot.

By the way, it seems that in actual use the input signal will be the voltage across a thermistor. In that case, your amplifier will have to be stable at DC.

Can you post the circuit in which your opamp is being used? Somebody might spot something, or at least it will give more clues as to what is happening and what can be done about it.

 

I have to build this from discrete components. It was difficult to simulate this circuit because ALD doesn't give accurate models for simulation. My simulation circuit required 4 P-channel MOSFET's to get enough current to balance. In the drawing M3 is the P-channel MOSFET. When I built the circuit I found that 4 P-channel MOSFET's drew too much current, so I removed 3 of them. Also, this op-amp will be one of two in a sample and hold circuit. I have a 0.1uF by-pass cap on the supply. Adding more caps there didn't change anything. I tried adding a by-pass capacitor at the gate of M4, but that just increased the noise to the entire signal. When I zoomed in on the noise it looks like its 2.38MHz with a 100Hz input signal.

 

I have to build this from discrete components.

Who says? Is this homework?

 

It is not noise. It is an oscillation.

Can you post the application circuit?

 

This is my senior design project. I thought I did post the schematic of the op-amp. I haven't connected it to the whole circuit yet because I haven't gotten it to work on it's own yet. I'll post the schematic again along with a picture of the breadboarded circuit.
.

 

I doubt anybody will be able to see how your opamp is connected from that photograph. A schematic might enable somebody to give you specific guidance.

 

A schematic is attached. I don't know how to post a thumbnail of the pdf file. For some reason I only got the option to post a thumbnail with that picture and not the pdf file.

 

That makes sense that it's oscillation and not noise, but why only that part of the signal? I converted the file to a jpg.

 

Anyone??

 

I notice in your picture that the MOSFET in row 25 has open pins on the left hand side (relative your photo), including the gate. I'm not sure how it is with this MOSFET, but that can cause problems for op-amps. I'm also wondering if a few bypass caps on the board would help. You don't even have one on the power rails. Just a thought. Oh, I just read your post #5. What about looking at the FFT as Dick suggested in #4?

 

I am just wondering why the OP expects this design to be unity gain stable.

 

I'm not sure the oscilloscope I'm using has that function, but I'll go to the lab on Monday and see.

Joeyd999, what does OP stand for? If this design isn't unity gain stable, then how do I make it so?

Thanks,
Mike

 

Joeyd999, what does OP stand for? If this design isn't unity gain stable, then how do I make it so?

OP = Original Poster (that means you). These days, seems that most use TS as in Thread Starter. I'm old school...I don't like change for the sake of it.

Read this.

 

That makes sense that it's oscillation and not noise, but why only that part of the signal? (some text removed for clarity)[/ATTACH]

Gain and delay (phase shift) are different at different DC levels in many circuits. Most likely, the combination of gain and phase shift are not enough to cause oscillation until the signal swings toward the lower end of the cycle.

Per joeyd999, You probably need to decrease loop gain.

 

I've uploaded a couple of images. One is an FFT from the gate of M4 and the other is an FFT from the gate of M8. I don't know if you can decipher the problem from these images. I'm able to get the maximum's of the signal to match with zero error, but then the minumum's will be off by around 64mV. I need an error of less than 10mV from each op-amp in the sample and hold circuit. It will be an 8-bit SAR ADC and that corresponds to a voltage of 20mV for the LSB.

 

sailmike>
I have to build this from discrete components. It was difficult to simulate this circuit because ALD doesn't give accurate models for simulation.

No. It is not true. The power N-channel transistor is less than 15 times compared to the datasheet (a spice-model).
sailmike. Give me the value of resistors. Please. I will try to simulate your circuit.

 

sailmike.
I did a simulation of your circuit.And I got generation. Additionally, I added a simulation with an oscilloscope probe. The oscillation frequency depends on the modes of transistors (R1, R2).