I have been tasked to design a multistage amplifier with the following specifications: Gain(V/V) = 30, Rin = 20 kohms, Rout < 25 ohms, Power supply = Dual +12V -12V, Max Symmetrical Swing > 9Vpp (peak-to-peak), lower 3dB down point < 200 Hz, Upper 3dB down point > 5 kHz, Rload = 200 ohms. I already have done the analysis for the gain and 3dB down point for the lower frequency as shown by the schematic I provided

I do have some doubts because the simulation in ltspice is not working for either the AC sweep as well as the transient response. Of course, the transistors given in the schematic are not the correct ones, I am using three 2N7000's which I have extracted the Kn and Vt parameters for each for more accurate analysis, however, I am not sure how to design for the upper 3dB down point, I am aware that I could place a capacitor from the gate to the drain to create dominant poles, however, I am not sure if I have to do this for all transistors or just one to create a single dominant pole. I mainly need suggestions or processes to design for the upper 3dB down point. Any help would be greatly appreciated!

Note: Suggestions and/or similar examples are preferable as I want to be able to design this amplifier on my own. Here I will also attach my analysis via Imgur:

http://imgur.com/a/Tqq92Pb

. Please refer to this analysis for any mistakes or errors. I understand that the values for each of the capacitors and resistors are not practically available, so I plan to use resistors and capacitor in series and/or parallel to get approximately close to my calculated component values.

 

I have been tasked to design a multistage amplifier with the following specifications: Gain(V/V) = 30, Rin = 20 kohms, Rout < 25 ohms, Power supply = Dual +12V -12V, Max Symmetrical Swing > 9Vpp (peak-to-peak), lower 3dB down point < 200 Hz, Upper 3dB down point > 5 kHz, Rload = 200 ohms. I already have done the analysis for the gain and 3dB down point for the lower frequency as shown by the schematic I providedView attachment 319958

I do have some doubts because the simulation in ltspice is not working for either the AC sweep as well as the transient response. Of course, the transistors given in the schematic are not the correct ones, I am using three 2N7000's which I have extracted the Kn and Vt parameters for each for more accurate analysis, however, I am not sure how to design for the upper 3dB down point, I am aware that I could place a capacitor from the gate to the drain to create dominant poles, however, I am not sure if I have to do this for all transistors or just one to create a single dominant pole. I mainly need suggestions or processes to design for the upper 3dB down point. Any help would be greatly appreciated!

Note: Suggestions and/or similar examples are preferable as I want to be able to design this amplifier on my own. Here I will also attach my analysis via Imgur:

http://imgur.com/a/Tqq92Pb

. Please refer to this analysis for any mistakes or errors. I understand that the values for each of the capacitors and resistors are not practically available, so I plan to use resistors and capacitor in series and/or parallel to get approximately close to my calculated component values.

If possible, could I receive suggestions on how to design the maximum symmetrical voltage swing of less than 9Vpp and how I must think ahead to achieve this specification? On a side note, the Kn and Vt values for each of the transistors I would be using, 2N7000, are roughly 0.200 mA/V^2 and 2.2V respectively. Another note, the reason for the R5, R11, R6, R8, R12, R7, R10 and R9 resistors is to get a specific bias point for each of the transistors which is why I have included them (33/33/33 of the total voltage supply) . This is my first multistage amplifier design, so I am not entirely familiar with how to go about the design process and how resistors and capacitors really affect my specifications. I have attached my analysis via Imgur.

 

Is this a Homework assignment ?
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Is this a Homework assignment ?
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Yes, its more so a project im taking up for a class.

 

I do have some doubts because the simulation in ltspice is not working for either the AC sweep as well as the transient response. Of course, the transistors given in the schematic are not the correct ones, I am using three 2N7000's

Hi grand,
Please post your LTS asc file.
E

 

Hi grand,
Please post your LTS asc file.
E

Here is the LTS file I used, keep in mind that I am using 2N7000 MOSFETs. In this file, I was not able to find these model files for the 2N7000 so I opted with the transistors in the LTS file.

 

I have been tasked to design a multistage amplifier with the following specifications: Gain(V/V) = 30, Rin = 20 kohms, Rout < 25 ohms, Power supply = Dual +12V -12V, Max Symmetrical Swing > 9Vpp (peak-to-peak), lower 3dB down point < 200 Hz, Upper 3dB down point > 5 kHz, Rload = 200 ohms. I already have done the analysis for the gain and 3dB down point for the lower frequency as shown by the schematic I providedView attachment 319958

I do have some doubts because the simulation in ltspice is not working for either the AC sweep as well as the transient response. Of course, the transistors given in the schematic are not the correct ones, I am using three 2N7000's which I have extracted the Kn and Vt parameters for each for more accurate analysis, however, I am not sure how to design for the upper 3dB down point, I am aware that I could place a capacitor from the gate to the drain to create dominant poles, however, I am not sure if I have to do this for all transistors or just one to create a single dominant pole. I mainly need suggestions or processes to design for the upper 3dB down point. Any help would be greatly appreciated!

Note: Suggestions and/or similar examples are preferable as I want to be able to design this amplifier on my own. Here I will also attach my analysis via Imgur:

http://imgur.com/a/Tqq92Pb

. Please refer to this analysis for any mistakes or errors. I understand that the values for each of the capacitors and resistors are not practically available, so I plan to use resistors and capacitor in series and/or parallel to get approximately close to my calculated component values.

Hi,

Usually when you have to create a 3db down point it is usually of first order, so doing that with just one stage is probably good enough. You may have to check that though to see if a first order cutoff is good enough for your assignment. Since frequency response is always an issue, doing that with the first stage is probably best.
Also, to get the maximum output voltage swing usually you bias the output stage to about one-half of Vcc.

I have some questions too though.
First, do you really need three stages? Also, why so many frequency selective sections (R's and C's) ?
Second, why the unusual values for the capacitors? Usually the gains and frequency points are created using standard value caps and adjusting the resistances to accommodate. That would give you some unusual resistance values, but then for a real life circuit you look for values that are close to the theoretically ideal values.

 

Upper 3dB down point > 5 kHz

I am not sure how to design for the upper 3dB down point

The requirement is for a 3db point of greater than 5KHz. This should not be a problem. As long as you use large enough coupling capacitors, it should be well above that.

It sounds to me like you are trying to lower it. Are you trying you make it equal to 5Khz?

 

Hi,

Usually when you have to create a 3db down point it is usually of first order, so doing that with just one stage is probably good enough. You may have to check that though to see if a first order cutoff is good enough for your assignment. Since frequency response is always an issue, doing that with the first stage is probably best.
Also, to get the maximum output voltage swing usually you bias the output stage to about one-half of Vcc.

I have some questions too though.
First, do you really need three stages? Also, why so many frequency selective sections (R's and C's) ?
Second, why the unusual values for the capacitors? Usually the gains and frequency points are created using standard value caps and adjusting the resistances to accommodate. That would give you some unusual resistance values, but then for a real life circuit you look for values that are close to the theoretically ideal values.

So the reason for the unusual component values is due to my design process, i solved for relatively small low frequency poles to achieve the lower 3dB down point specification. The resistors values are due to my bias points of each transistor. The reason for the three stages was to get minimal distortion at the output. An important not is that I did redesign my circuit to something that fits my specifications more accurately. Refer to the image attached. I modeled the transistors in cadence and it’s working fine in terms of my specification, however, for the lower frequency 3dB down point as well as my high frequency down point, they are not close to where I designed them to be but still exceed. Is my understanding of the amplifier frequency response incorrect because I expected my lower 3dB down point to be at about 147 Hz and my upper 3 dB down point to be at about 10MHz. However, if you look at my frequency response simulation it is not accurate. Could you maybe clarify how frequency works and the general process for design?

 

The requirement is for a 3db point of greater than 5KHz. This should not be a problem. As long as you use large enough coupling capacitors, it should be well above that.

It sounds to me like you are trying to lower it. Are you trying you make it equal to 5Khz?

I am trying to lower it but not to 5kHz. My function generator only goes up to 20MHz and I want to ensure when testing my actual circuit, I can get a full frequency response measurement without exceeding the maximum frequency from my function generator. If you refer to my reply to MrAl, I have attached a new design and it meets what I wanted to do, but it does not match up to my design calculation.

 

So the reason for the unusual component values is due to my design process, i solved for relatively small low frequency poles to achieve the lower 3dB down point specification. The resistors values are due to my bias points of each transistor. The reason for the three stages was to get minimal distortion at the output. An important not is that I did redesign my circuit to something that fits my specifications more accurately. Refer to the image attached. I modeled the transistors in cadence and it’s working fine in terms of my specification, however, for the lower frequency 3dB down point as well as my high frequency down point, they are not close to where I designed them to be but still exceed. Is my understanding of the amplifier frequency response incorrect because I expected my lower 3dB down point to be at about 147 Hz and my upper 3 dB down point to be at about 10MHz. However, if you look at my frequency response simulation it is not accurate. Could you maybe clarify how frequency works and the general process for design?

Well you have these frequency selective networks:
[1] R16, R0, R14, C0
[2] R2, R3, C4,
[3] R1, C1, R4, R9, C6
[4] R6, R7, C5
[5] R5, C2, R8, R10
[6] R12, C3, R15

How did you come up with those values in order to meet the frequency requirements?

The frequency selection is basically based on if the cap is in series with the signal or in parallel. If it is in parallel, it acts on the higher frequencies to cut at some upper frequency, and if in series it acts on the lower frequencies to cut at some lower frequency.
Thus, to increase the higher frequency cutoff you would reduce the capacitor values of those in parallel and/or increase those in series. To decrease the higher frequency cutoffs you would increase the value of the caps in parallel and/or decrease those caps in series.
For the low frequency cutoff, to increase the low frequency cutoff you would decrease the parallel cap values and/or increase the series cap values.
To decrease the low frequency cutoff do the opposite.
To do both you would probably be able to adjust the parallel caps for the high frequency cutoff and adjust the series caps for the low frequency cutoff.

However, since you have so many frequency selective networks it would somewhat of a system goal, where you may want to try to optimize them to some reasonable requirement. That's why I wanted to know how you came up with the values that you already have for the resistors and capacitors. Since they all play a part in the AC gain, you have to know the transfer function that includes every resistor and every capacitor, and whatever model you are using for the MOSFET's for your hand calculations.

A question then is, what model are you using for the MOSFET's, and how did you come up with the values in the schematic so far.

 

Well you have these frequency selective networks:
[1] R16, R0, R14, C0
[2] R2, R3, C4,
[3] R1, C1, R4, R9, C6
[4] R6, R7, C5
[5] R5, C2, R8, R10
[6] R12, C3, R15

How did you come up with those values in order to meet the frequency requirements?

The frequency selection is basically based on if the cap is in series with the signal or in parallel. If it is in parallel, it acts on the higher frequencies to cut at some upper frequency, and if in series it acts on the lower frequencies to cut at some lower frequency.
Thus, to increase the higher frequency cutoff you would reduce the capacitor values of those in parallel and/or increase those in series. To decrease the higher frequency cutoffs you would increase the value of the caps in parallel and/or decrease those caps in series.
For the low frequency cutoff, to increase the low frequency cutoff you would decrease the parallel cap values and/or increase the series cap values.
To decrease the low frequency cutoff do the opposite.
To do both you would probably be able to adjust the parallel caps for the high frequency cutoff and adjust the series caps for the low frequency cutoff.

However, since you have so many frequency selective networks it would somewhat of a system goal, where you may want to try to optimize them to some reasonable requirement. That's why I wanted to know how you came up with the values that you already have for the resistors and capacitors. Since they all play a part in the AC gain, you have to know the transfer function that includes every resistor and every capacitor, and whatever model you are using for the MOSFET's for your hand calculations.

A question then is, what model are you using for the MOSFET's, and how did you come up with the values in the schematic so far.

So i am using some model files i created, where i extracted the MOSFET parameters of each transistor to get a more accurate response in terms of how the amplifier would behave in real life. I did not know that all the RC networks played a role in the frequency response for both the upper and lower down points, in hindsight I should have known that. So for the networks themselves, the resistor values all came from the biasing points for each transistor. For the source degeneration resistors, i simply just designed for a specific gain of that stage and found what rss had to be for each of the CS stages. For the capacitor values, i used the low frequency pole analysis to solve for each of the values for the bypass/coupling capacitors in the networks, refer to the work i attached on imgur in the original post. However, I will look into the transfer functions of each stage and make design decisions accordingly. Although, would i make the transfer functions for each transistor individually as if they are not cascaded?

 

So i am using some model files i created, where i extracted the MOSFET parameters of each transistor to get a more accurate response in terms of how the amplifier would behave in real life. I did not know that all the RC networks played a role in the frequency response for both the upper and lower down points, in hindsight I should have known that. So for the networks themselves, the resistor values all came from the biasing points for each transistor. For the source degeneration resistors, i simply just designed for a specific gain of that stage and found what rss had to be for each of the CS stages. For the capacitor values, i used the low frequency pole analysis to solve for each of the values for the bypass/coupling capacitors in the networks, refer to the work i attached on imgur in the original post. However, I will look into the transfer functions of each stage and make design decisions accordingly. Although, would i make the transfer functions for each transistor individually as if they are not cascaded?

Hi,

Yes, usually all the components play a part in the frequency behavior, unless maybe there are no capacitors and everything is DC coupled and the frequency is not too high where the transistors themselves start to limit the response.

When you say you designed the source resistors for a specific gain, how did you do that without considering the effect of the source capacitors, which would be frequency selective? Did you just consider one frequency, but if so, how did it not occur to you that when the frequency changed the gain would change.
It's ok if you missed something, I am just trying to figure out exactly what you did to get this far, that's all, and I am not saying you did anything wrong either, just want to follow your work up to this point.

I'll check out your original post again...

Ok, I checked out your linked page with the hand drawn schematic and design notes. Unfortunately, the hand writing is not very good so it's just too hard to read when trying to follow your work. You would have to type that out so it can be read more easily. In some places I can't even tell what you have written because it looks so cryptic. Maybe you could write that over again only a little neater, or actually a lot neater. You probably don't have to type the whole thing just start with one section and we can take a look that that first. For example, the first section or something, or even the last section.
It would be good if you could show the model you are using for the MOSFET's too.
Please type out everything you possibly can, or write very neatly so that everything can be read easily. This will make this go a lot faster too.