Hi I am trying to drive Half bridge converter using IR2101 and MOSFET SIHG20N50C-E3.

The voltage i need at the output is 100Volt . at my first attempt i vary my voltage until 72volt and it vary nicely with some noise. after that high side mosfet spoil .followed by IR2101 , and optocoupler which is connected to TL494.

I replace the mosfet , IR2101 and isolator , now the condition is it can go upto 16volt after that mosfet is spoiled again

Please help me to figure out the issue

 

Schematic?

 

Schematic?

Frequency is 100khz , current is 1.5amps

 

With this setup you need to make sure that the high side fet never stays on for a long time, and that you have enough dead time between the top closing and bottom opening and vice versa.
Out of curiosity, what kind of software did you use for that schematic?

 

As kubeek said, the input signals need to be have a dead time so that both transistors aren't momentarily on at the same time.
How you generating the signals?

 

With this setup you need to make sure that the high side fet never stays on for a long time, and that you have enough dead time between the top closing and bottom opening and vice versa.
Out of curiosity, what kind of software did you use for that schematic?

* Software is cadstar
* But first the circuit was working upto 72volt, once break down occur it is not going above 16 volt ,I tried three times , 3 times also same high side mosfet blown with driver and isolator . and I believe if dead time is the issue both mosfet will blow

 

As kubeek said, the input signals need to be have a dead time so that both transistors aren't momentarily on at the same time.
How you generating the signals?

* signals are generating using TL494

 

"kubeek, post: 1002938, member: 4023"]With this setup you need to make sure that the high side fet never stays on for a long time, and that you have enough dead time between the top closing and bottom opening and vice versa.
Out of curiosity, what kind of software did you use for that schematic?[/QUOTE]

The wave form for the mosfet gate pulse
Does it looks good, green is the high side pulse

 

* signals are generating using TL494

I meant what is generating the signals to the TL494?

The signals you posted have no overlap between when the green signal goes low and the yellow signal goes low. There needs to be a non-overlap time between those two.

Only one MOSFET will blow (the one dissipating the most power during the time they are both ON).

 

The signals you posted have no overlap between when the green signal goes low and the yellow signal goes low. There needs to be a non-overlap time between those two.

Actually I don´t think they do, he is measuring the voltage at the gate, not Vgs, so there seems to be roughly 3us of deadtime. However the edges look really slow.
Why do you have 20 ohm resistor between gate and source? That looks like a really bad move, that should in the order of 10K.
And more to the point, why is that a completely different schematic than before?

 

Hi 20 ohm resistor form gate to source is incorrect its 1kohm resistor .
After the above schematic i modify , try to add some snubber .
regarding the dead time, is 3us is enough dead time or do i need to increase more .

If i dont give the Bus voltage the waveform is like Print 001. and when i give the bus voltage the waveform looks like print 000a.
i worried about the red portion in the pic , is it normal

Even after adding the snubber the circuit cant go above 42volt., anything else i need to try again

 

I meant what is generating the signals to the TL494?

The signals you posted have no overlap between when the green signal goes low and the yellow signal goes low. There needs to be a non-overlap time between those two.

Only one MOSFET will blow (the one dissipating the most power during the time they are both ON).

Hi crutschow
Signals are generated by TL494 itself depends upon the feedback of voltage and the frequency . I hope this is what you are expecting .
May i know what is non overlap time . is that the dead time you mean .
the waveform i posted above is gate pulse of the mosfet .
May i know which waveform you want

 

Actually I don´t think they do, he is measuring the voltage at the gate, not Vgs, so there seems to be roughly 3us of deadtime. .................

True when the yellow signal goes low and the green goes high, but not when yellow goes high and green goes low.

 

True when the yellow signal goes low and the green goes high, but not when yellow goes high and green goes low.

Hi crutschow
Can you please explain what is the difference between these two situation.
from my understanding if there is problem of interchanging the signal it will show when the circuit on.
But now circuit can work until 2volt to 42volt ( by changing the voltage at the TL494 input ) above that only the driver and the mosfet burns
# So from your point do i need to interchange the signal

 

..............
# So from your point do i need to interchange the signal

No.
You need to provide a non-overlap time for both transition points, not just one.
Thus the green must go low before the yellow goes high (only one signal high at a time).

The circuit burns at higher voltage because the current spike and dissipation increases with voltage.
At some point the dissipation becomes high enough to zap the device.

 

No.
You need to provide a non-overlap time for both transition points, not just one.
Thus the green must go low before the yellow goes high (only one signal high at a time).

I still think the green does go low before the yellow goes high, but it it riding on the output voltage so it looks as if it did not.
If we knew what the output load was things would be much easier.

 

No.
You need to provide a non-overlap time for both transition points, not just one.
Thus the green must go low before the yellow goes high (only one signal high at a time).

The circuit burns at higher voltage because the current spike and dissipation increases with voltage.
At some point the dissipation becomes high enough to zap the device.

Hi
Can you please explain more about , "non overlap time for both transition points"
With my starting knowledge in this field , and with how i prob what my understanding is Green is highside mofet and Yellow is lowside mosfet
So 'the green must go low before the yellow goes high" mean There is should be dead time ( Non overlap time from My understanding ) after high side mosfet Turn OFF and Low side MOSFET Turn ON

Considering that scenario Print 001 is satisfying where as Print 000a is not fulfilling the condition

Am i right , if any change please high light

 

I still think the green does go low before the yellow goes high, but it it riding on the output voltage so it looks as if it did not.
If we knew what the output load was things would be much easier.

Hi
the output load now i given is resistive load 10kohms , so at output not much current is flowing .
from the waveform i think pink high lighted portion is inductor voltage . since i dont have differential prob i cant get the waveform for high and low at the same time . but when i prob with respect to source the gate voltage is normal as in Print _001a

 

I still think the green does go low before the yellow goes high, but it it riding on the output voltage so it looks as if it did not.
.....................

I see what you are saying. The top transistor (green trace) turns off when the voltage drops, but doesn't go to zero until the bottom transistor turns on.
If that's true then there would seem to be no overlap or shoot-through problem.

 

This looks more like an implementation problem than design. How close is the driver IC to your power FETs? The connection between the lower FET source terminal and the ground pin on the IC is particularly critical in using these drivers. Nanosecond pulses can easily be generated with interconnects a few inches long, and these pulses can exceed the maximum rated terminal voltages of the IC. Using a solid ground plane with the IC ground pin and FET source pin directly soldered is best. I would remove the 20 ohm resistors and replace them with 12 volt 1 watt zener diodes soldered right at the FET pins.
Another passing comment is that if you absolutely do not need 100khz drop the frequency. If you can use 50khz you make everything half as critical! If you can use 20khz you may not even need heatsinks on the FETs! The physical size will usually not be enough larger to make any difference in most applications. Just a thought from an engineer with many years of experience.