I have to following code for a Mux and it complies. When I go to the wave form it simulates perfectly. Thing is, I do not know what I am looking for, to see if it is correct.

Here is the code

Library ieee;
Use ieee.std_logic_1164.all;

Library ieee;
Use ieee.std_logic_1164.all;

Entity Mux is
Port(
D : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic);
End Mux;

Architecture Joe_Structure of Mux is
Begin
with S select
Y<= D(0) when "00",
D(1) when "01",
D(2) when "10",
D(3) when "11";
End Joe_Structure;

 

Do you understand how a MUX works? If you do then you should be able to see from the timing waveforms if the operation is working properly or not.

 

You're look for:

Y = D(0) when S = "00",
    D(1) when S = "01",
    D(2) when S = "10",
    D(3) when S = "11";

 

what you're missing is a TEST-BENCH -
Another code which has your MUX as a component, and generates clock and reset (you can skip it because it's an Asynchronous module, your mux), and changes the inputs to your mux, and checks its outputs....(that's why you DO need clock and reset, for the changing it time)
Have fun.