Hello,
I want to calculate the input impedance of a circuit, equations below, to define its equivalent scheme in low frequency (resistance) and high frequency (capacitance or inductance). But when I try to do the calculations I find equations very complicated when I take into consideration the technological parameters of the transistors NPN and NMOS.

Can you help me in my calculation to find the right equation simplified equivalent impedance? And can you tell me that they are the technological parameters that I can neglect compared to others?

Thank you very much.

 

Can you show us the circuit? If it is not the secret.

 

Hi,

You might also show what kind of application this is to be used in. Often the application has a lot to do with the kind of approximations you can use are. For example in one app you may be able to use 10 percent tolerance resistors, but in another app you have to use 0.1 percent resistors, which is a BIG difference as you can see.

With bipolar transistors a typical approximation is to use a current controlled current source or voltage controlled current source in place of the transistor. If there is a concern about frequency roll off, you can add a single pole filter. In more critical apps though you have to use the small signal model anyway.

Some analyses are more complex than others, that's just the way it goes, but what you can get away with depends on how much simpler you can make it without loosing too much generality or accuracy.
These concepts are often combined with the design during the design process so that you can help to make the circuit less sensitive to component variations and that also usually makes the analysis simpler as well.

 

Hello,
Sorry for my late reply. I want to calculate the impedance at the bound of in for the attached circuit.
Also, I would like to know when I can neglect the equivalent impedance of the transistor Q1 in front of others? And when I can consider the base of Q1 connected to a virtual ground?
Thank you for your help.

 

Hi,

Real quick, this looks like a circuit where you have to consider the DC voltage levels and cant ignore the base emitter voltages. That means you probably have to use the voltage controlled current source model of the transistor, or even the spice model really.

Others here may wish to chime in with more information.

 

you probably have to use the voltage controlled current source model of the transistor,

Actually you want the current-controlled current-source model to calculate the bias point, not the voltage-controlled (transconductance) model which is usually used for AC analysis.
Thus you use the current gain (Beta or hFE ) value of the transistor with an estimated value of the base-emitter voltage (usually about 0.65-0.7V).

In the op's circuit the base-emitter voltages of Q1 and Q2 basically cancel so that simplifies the bias calculations.

 

Your equations in post #1 show a number of parasitic components (resistances such as rbb and various capacitances) which you will need to include if you want to get the same equations you show in post #1.