Hello everyone,

I'm attempting to create an SPI circuit for my retro 8085 development kit.
I've successfully implemented a "bit-bang" method using SID/SOD and an IO port
but I really wanted to create a high speed port to interface to an SDCARD via SPI.

The circuit schematic I created is attached and is currently implemented on my breadboard and seems to work fine.
I have attached the wave forms output at an SDCARD for both my circuit and one I captured from an Arduino/SD Card
test rig.

After sending the CMD0 command, I should see a response of "01" from the card, however I am not getting anything back on the MISO
line except a constant "1". On the Arduino waveform you can see the response after the CMD0 command, , however my waveform is not getting it.
Now, my thinking is that I am using too high of a bitrate (2MHz) while the Arduino is using about 260KHz. If this is true , then I need to slow down the clock rate for the shifter (74ls299) and the counter (74ls390) . However, simply slowing the clock will mess up the timing between the 8085 and the 74ls299.

Is this design doomed or can it be salvaged? It seems like I am sooo close, but oh so far.
Can any of you experts give me a hand? It would be much appreciated.
thanks

 

Yes, you need to slow the SPI clock speed down. You should be able to find cards that initialize at 500 kHz so you can clock the CPU during that time at the same clock speed reduction ratio.

 

Yes, you need to slow the SPI clock speed down. You should be able to find cards that initialize at 500 kHz so you can clock the CPU during that time at the same clock speed reduction ratio.

Thanks for the response NSASpook,
If I slow the CLOCK down, it will mess up the timing of the parallel load/output of the 299. The same clock is being used
to shift the bits as well as the load/output to the 8085 bus.
It seems I need 2 clocks, but the 299 only has 1 clock input.
I've also considered a latch between the 8085 data bus and the 299. That would add some complexity I was hoping to avoid.
Any ideas?
thanks

 

I guess I'm missing something here on how you handle the I/O.
I'm not sure what the timing issue is if the 8085 CPU clock is reduced by the same factor as the SPI clock during the SDCARD init phase.

 

I guess I'm missing something here on how you handle the I/O.
I'm not sure what the timing issue is if the 8085 CPU clock is reduced by the same factor as the SPI clock during the SDCARD init phase.

The CLOCK coming from the 8085 CPU is 2MHz. I can't modify the PU clock, I can only work with the 2MHz from the expansion bus. The 299 needs to do a load and save to the 8085 Data Bus. The 8085 is going to expect timing to be sync'd to its own 2Mhz clock.
If I simply divide the clock down to 500KHz, the 299 will not load from the data bus fast enough, nor will it output to the data bus fast enough.

I hope I am explaining this ok. I'm rather an amateur at circuits.
thanks for the help though,
cheers

 

The CLOCK coming from the 8085 CPU is 2MHz. I can't modify the PU clock, I can only work with the 2MHz from the expansion bus. The 299 needs to do a load and save to the 8085 Data Bus. The 8085 is going to expect timing to be sync'd to its own 2Mhz clock.
If I simply divide the clock down to 500KHz, the 299 will not load from the data bus fast enough, nor will it output to the data bus fast enough.

I hope I am explaining this ok. I'm rather an amateur at circuits.
thanks for the help though,
cheers

OK, you can't (with the current design) modify the speed of the CPU clock and your SPI logic is designed to be synchronous with the CPU clock. Sounds like you're in a pickle with this design limitation that doesn't use a interrupt or a 'ready' CPU wait signal to allow for asynchronous transfers.

https://nptel.ac.in/courses/108107029/module3/lecture11.pdf