Hello, I'm trying to sketch a transistor-level schematic for a CMOS 3-input XOR gate, and am unsure about how to go about doing this. I know that the basic equation for a 3-input XOR is:

Y = ABC + A'B'C + A'BC' + AB'C' (where Y is output)

But I'm unsure on exactly how to arrange the nFETs and pFETs to design this system. Can someone please help me?

 

Can anybody help please? Anyone at all?

 

I would like to look at that to see if I can offer anything useful, so that I have to think about it and will learn something new whilst hopefylly helping.
I have never seen the kind of sketch you are talking about ....
Are pulup resistors and diodes are permitted.
Can you give an example of the 'sort' of thing you are talking about?
Al

 

Do you know of a chip name that is all XOR gates.

Example- CD4001 is a chip with NOR gates. Looking up the data sheet will usually net you a 'schematic' of the chip. Looking at how the BigBoys designed the chip will be sure to give one ideas on how to proceed.

 

Can anybody help please? Anyone at all?

Take the logic circuit for the gate then find the transistor level equvalents of the internal gates.

http://www.google.com/search?btnG=1&pws=0&q=3-input+XOR+gate

 

mmmmm I just learned what TTl, RTL, DTL and CMOS is all about ... OK not all.
I expect you mean like this then.....
http://www.play-hookey.com/digital/electronics/cmos_gates.html
That would imply some basic rules for the actual transistor layout.
Dont stack more than 4 transistors
Buffer the output, twice to jeep the base function and once to invert it.

Is that what you are looking for? Obviously with the 3-XOR logic though.
Al

 

http://www.eng.cam.ac.uk/DesignOffice/mdp/electric_web/Digital/DIGI_3.html

Spend 20 minutes reading this and it will help you out.

Psst! CD4070 is an XOR chip

 

http://pdf1.alldatasheet.com/datasheet-pdf/view/26894/TI/CD4070.html

 

OK, Interesting read, simmilar info on the play-hookey site.
I suspect that the answer needs to be in terms of the basic transistor level blocks:-
NOT / NOR / NAND
These couldnt be more than 4 inputs wide without cascading blocks.
The equation in the question is probably the key to the best transistor layout.
what do the symbols mean? have I got the following correct?
(B') is NOT B, (AB) is A AND B, (A + B) A OR B.
if that not correct and / or if there are others I would apriciate someone putting me right.
Al

 

Just tested that supersition out on a spreadsheet and it dosnt stack up unless I change the equation to:-
Y = A'B'C' + A'B'C + A'BC' + AB'C'
At this point I think it is far more likley that I am wrong and the origional equation is correct.
What am I missing guys?

 

Just tested that supersition out on a spreadsheet and it dosnt stack up unless I change the equation to:-
Y = A'B'C' + A'B'C + A'BC' + AB'C'
At this point I think it is far more likley that I am wrong and the origional equation is correct.
What am I missing guys?

The output is high when ONE of the three inputs is high, but low for any other combo.

 

Yes I know that ..... its not the logic I dont understand its the notation.
The origional question quoted:-
Y = ABC + A'B'C + A'BC' + AB'C'
I am not familiar with the notation and asumed:-
+ means OR
Q' means NOT Q
QR means Q AND R
When I tested my asumption the equation didnt form a 3 input XOR, there was 1 faulty input state.
However... Y = A'B'C' + A'B'C + A'BC' + AB'C' is correct if my asumption is correct.
but
If Y = ABC + A'B'C + A'BC' + AB'C' was right in the first place then I'm not and I need to learn a bit more!!
Al

 

With four terms in the boolean equation - how would it form a 3 input circuit?

The last three boolean statements are correct for a 3 input XOR, but the first one;whether its ABC or A'B'C' is not a true statement for XOR logic - so

Now you are confusing me

 

Yes your right, omitting the first 'block' thus:-
Y = A'B'C + A'BC' + AB'C'
maintains / creates the XOR condition, asuming the notation means what I 'think' it means so my question still stands.

Is this:- (From the origional post)
Y = ABC + A'B'C + A'BC' + AB'C'
valid XOR notation that I dont understand how to read.
OR
Am I reading it correctly making this:-
Y = A'B'C + A'BC' + AB'C' (as you stated)
correct,
and this:-Y = A'B'C' + A'B'C + A'BC' + AB'C' (my initial tweek)
valid but containing an AND block that isnt required to achieve the desired end result?

As I said ....... Am I reading the notation correctly?

I am asking -because- it dosnt 'appear' to make much sense to me either, unless, as is entirly possible at this point, I am missing something and interpreting the equation incorrectly.

Al

 

To Dyslexicbloke and Kermit 2: What I meant in the original post was that the apostrophes (') mean "NOT" so A' is NOT A. And yes, the + means OR and AB means A AND B. Sorry for any confusion.

The truth table for a 3-input XOR as far as I know is:

(where the output is only 1 if there are an odd number of high inputs).


To all:
Thanks for the responses so far. The only things I really want to use in this transistor-level schematic are VDD source, Ground, inputs, output, pFETs and nFETs. On PSpice, I've created a transistor-level schematic for what I mean by 2-input CMOS XOR gate (the top voltage source is simply supposed to be Vdd of 5V, ignore the missing connection):

Now all I need to know is how to align the transistors to make a 3-input version of exactly this, lol.

 

OK …. So take a look at these, I think the second one from kermit2 is probably the better of the two.
The only thing I noticed in the first one that I didn’t ‘notice’ in the second was a reference to a maximum of 4 series transistors per gate, but I only skim read it to be fair.
http://www.play-hookey.com/digital/e...mos_gates.html
http://www.eng.cam.ac.uk/DesignOffic...al/DIGI_3.html

It would appear that :- Y = A'B'C + A'BC' + AB'C' is correct rather than the :- Y = ABC + A'B'C + A'BC' + AB'C' that you originally stated so if you take that and then build it from the ‘standard’ gates in the above articles you will be there.

Obviously you will need to modify the NAND arrangement to be 3 wide and invert one of it inputs for each block.
Three of these will then be OR’d and buffered to complete a standard B series 3 input XOR.

I would suggest building it on a spreadsheet, using worksheet functions in formulae first to check if your design is correct before you start to draw it up.
PLEASE REMEMBER ....

I am no wiser than you here and learning as I go so don’t take anything I have said as fact.
I am just posing a possible approach to solving the problem that seems logical to me right now.
I will be watching to see if I was anywhere near right.
Al

 

I'm sorry for such a long delay, but the solution to my problem (schematic for 3-input XOR) turned out to be as follows:

Thanks to everyone who helped out.