Help implementing some digital logic for a power supply control system

Thread Starter

SiCEngineer

Joined May 22, 2019
223
I am looking to implement a type of dual control system, which enters hysteretic pulse control at no load and exits and uses PI control at full load. The trigger to indicate when the load is transitioning from full load to zero load and back is available to me if desired.

I have at the moment designed the comparators and assumed I will need an SR flip-flop, which will retain the 10 or 01 state depending on whether the upper or lower limit was the last to be reached. I now do not know where to go next. The algorithm I want to implement is as follows:

If Q,!Q = 10, (V = Vlower), turn on the switches until LOAD PULSE = 1 (0mA) or Q,!Q transitions to 01, indicating the upper limit has been reached.
Keep the switches off, until the LOAD PULSE = 0 (full load), or the flip-flop transitions to 10, indicating the lower limit has been reached.

I'm sorry that this is a very application specific question but I have been struggling with it for a while for some reason. Everything I try seems to give the wrong result.
 

MrChips

Joined Oct 2, 2009
21,686
In order to communicate your requirements more clearly, do the following.

1) List all input signals.
2) Name the output signal.
3) Draw a timing diagram showing the time/logic relationship between inputs and output.
 

Thread Starter

SiCEngineer

Joined May 22, 2019
223
In order to communicate your requirements more clearly, do the following.

1) List all input signals.
2) Name the output signal.
3) Draw a timing diagram showing the time/logic relationship between inputs and output.
The input signals are the two hysteretic comparators, one which triggers to a 1 when the lower limit is reached, and the other triggers to a 1 when the upper limit is reached. Between the values they are both 0. I also have an input signal which indicates whether the load is transitioning from full load to zero load, or from zero load to full load. 1 Indicates no load, 0 indicates full load.

The output is the drive signals for the half-bridges of a resonant network. Pulsed off when the load current = 0A, only turned back on if the pulse is removed or the lower voltage is reached. They are then turned back off if the load current signal is turned on and the cycle repeats.

Unfortunately, I do not know how I would draw a timing network as I have yet to implement the logic that I want? Or have I misunderstood?
 

MrChips

Joined Oct 2, 2009
21,686
Unfortunately, I do not know how I would draw a timing network as I have yet to implement the logic that I want? Or have I misunderstood?
Yes, you misunderstand. You have it backwards. You design the logic after you decide how you want it to behave. That is the purpose of the timing diagram. It is like drawing a route on a map showing where you want to go. The mode of transportation is to be decided after you choose the route you want to take.

Here is how to draw a timing diagram.

1) You have an input 1 signal coming from a comparator that goes from low-to-high when the lower limit is reached. Draw that.
Farther below show what is supposed to happen on the output of the digital circuit that you are yet to design.

2) Below the first line in (1) show the input 2 coming from the second comparator that goes from low-to-high when the upper limit is reached. Modify what is suppose to happen the output to show this outcome

3) Add below the line in (2) add the load transition signal input 3. Modify the output to show this effect.

Timing Diagram Example.jpg
 

Thread Starter

SiCEngineer

Joined May 22, 2019
223
Okay, think I understand, thanks for your help thus far. I have attempted to make a timing diagram, see attached. The application is for a resonant converter, and I am trying to implement a kind of pulse skipping technique at no load to allow regulation. The output is pulsed at varying duty cycles and frequencies, which I have knowledge of. This is shown in the diagram. Also shown is the output voltage, which must be kept between two upper and lower limits during transients.

Inputs: Comparator 1, comparator 2, and the load pulse. Outputs: Output voltage and MOSFET half bridge switchesIMG_20200206_112522.jpg
 

MrChips

Joined Oct 2, 2009
21,686
As they say, a picture is worth a thousand words.
It is still not clear from your description what is supposed to happen. Here I have drawn my interpretation of what you have described. I do not understand the behaviour and effects of the third input.

Timing Diagram Example 2.jpg
 

Thread Starter

SiCEngineer

Joined May 22, 2019
223
As they say, a picture is worth a thousand words.
It is still not clear from your description what is supposed to happen. Here I have drawn my interpretation of what you have described. I do not understand the behaviour and effects of the third input.
The third input is the load pulse. When it is triggered on, the switches should turn OFF, causing the output voltage to fall. The switheches should only turn back on if this goes LOW, or if the bottom voltage limit is reached. WHich software did you use for this diagram?
 

Thread Starter

SiCEngineer

Joined May 22, 2019
223
I use a simple draw program.

Here is how I understand it.
I believe this is right, if you have switched the polarity of the output? As when the output is OFF, the voltage should drop. But I think this is what you have done. So I think it looks right.

EDIT: Actually, the output being 1 means that the switches are ON. Therefore I think that the output should be HIGH more than it is shown in the diagram. For example it should be ON until the load is pulsed ON, in which the switches should turn OFF until the lower voltage limit is reached, or the load is pulsed OFF.
 
Last edited:

MrChips

Joined Oct 2, 2009
21,686
Ignore the logic LOW/HIGH for now. This can be altered later.
We work with what is known as POSITIVE LOGIC. This means that a positive action is represented by 1 or HIGH.

In words,

1) A logic 1 on the LOW LEVEL COMPARATOR detect sets the output to 1.
2) A logic 1 on the HIGH LEVEL COMPARATOR detect resets the output to 0.
3) A logic 1 on the LOAD signal resets the output to 0 unless if (1) is present.

For example it should be ON until the load is pulsed ON, in which the switches should turn OFF until the lower voltage limit is reached, or the load is pulsed OFF.
Can you clarify what you mean by the last statement hilited in red?
 

Thread Starter

SiCEngineer

Joined May 22, 2019
223
Ignore the logic LOW/HIGH for now. This can be altered later.
We work with what is known as POSITIVE LOGIC. This means that a positive action is represented by 1 or HIGH.

In words,

1) A logic 1 on the LOW LEVEL COMPARATOR detect sets the output to 1.
2) A logic 1 on the HIGH LEVEL COMPARATOR detect resets the output to 0.
3) A logic 1 on the LOAD signal resets the output to 0 unless if (1) is present.


Can you clarify what you mean by the last statement hilited in red?
The load is pulsed ON and OFF at a predetermined frequency and duty cycle. Going from full load (signal is a 0) to zero amps load (signal is a 1). When the load is pulsed OFF (signal is a 1), the switches should be turned OFF as well, because in resonant converters this would otherwise cause a large voltage increase which is unacceptable. The switches should only be turned back ON when the lower voltage limit is reached (we need to deliver some energy to the load) or the load signal is pulsed OFF (meaning we have returned back to full load). Hope that makes sense.
 

MrChips

Joined Oct 2, 2009
21,686
Sorry, I cannot make any sense of what you are saying.

1) "Going from full load (signal is a 0) to zero amps load (signal is a 1)." What signal?

2) "When the load is pulsed OFF (signal is a 1), " What do you mean by pulsed OFF. What signal?

3) "The switches should only be turned back ON" What switches? How many different output signals are there?

4) "or the load signal is pulsed OFF" What do you mean by pulsed?

In electronics, we make a distinction between a pulse and steady stated (or level).

I cannot proceed with the timing diagram until this is perfectly clear. I cannot tell if there is a single output or if there is a second output called SWITCHES.


Here are some terms we use when describing signals.

Rising edge can also be described as a low-to-high transition.
Falling edge would be a high-to-low transition.

High pulse can be called positive transient.
Low pulse would be a negative (going) transient.

As I said, we do not confuscate things by using negative logic. We think in positive signals and then change them when it comes to actual implementation. Hence to turn on the power we use a HIGH signal.
Timing Diagram Example 4.jpg
 

Thread Starter

SiCEngineer

Joined May 22, 2019
223
As I said in my previous comments the load signal is an external signal that is available for the control system, and it indicates whether the converter will be operating in full load or no load. This relates to question 1 2 and 4. When it is a 1, the load transitions from full load to zero load (and I then want to make control system changes according to this). When it transitions to a 0, the load current returns to full load value.

The switches I say because there are two half bridge switches connected to the LCC network.
 
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