Does anyone have any ideas on how to create an adjustable analog delay (up to 150uS delay ) for analog signals in the dc to 20khz ,0-5V range , accurately delaying the signal with no amplitude degradation and linear phase. im trying to simultaneously sample current and voltage of a signal and the allegro acsxxx series current monitor ic has about a 6us i/o delay. I have to delay the voltage sensing op amp signal so i can multiply the two V&I samples together to calculate power. Obviously the samples must be exactly in phase to be accurate. Signals are sampled into an adafruit m4 microcontroller with internal adc's which i want to use and there is an additional delay of about 90uS between the 2 adc reads that i have to compensate for (so about 100uS total) . i could do it digitally with external adc's triggered the 6us apart but that would add cost, was hoping there would be some way to do this in the analog realm so i could use the onboard adc's but i am not finding any solutions. i can't time align the signal digitally in software because my samplerate will only be about 5Khz so can only have a 200us dither which is way too coarse. The largest Adjustable delay step size tolerable is about 400nS (preferably lower) which would give me about 5% error at 20khz ( if my calcs aren't wrong) so i need delay adjustments to this resolution or better. ideas?

 

Welcome to AAC!

The only solutions I can offer with such long delay times are an analog bucket brigade or an ADC/memory/DAC solution.

 

can't time align the signal digitally in software because my samplerate will only be about 5Khz

I'm confused.
How do you expect to process 20kHz signals with a 5kHz sample rate which, according to the Nyquist criteria, can only digitize signals up to 2.5kHz maximum.
Frequencies above that will be aliased into lower frequencies (difference frequency between the high frequency and 1/2 the sampling rate).

To digitize 20kHz signals you need a sample rat of at least 40kHz ( for example, audio CDs use 44.1kHz).

 

its a long term average with tens of thousands of samples so after averaging it does very well , it actually works for signals higher than 20k , nyquist doesnt apply to long term averaging with undersampling, im not trying to recreate or store waveforms and capture transients accurately, in which case you are right i would need much higher samplerate more like 10x the max freq, instead i am doing longterm (relatively) averages where despite the low sr i get enough points that land on peaks etc that i can accurately average

 

l already looked into bucket brigades and they have too long of delay (100ms) so i need a magnitude shorter unless ive missed a faster one in my diggings

 

How about 2 analog sample and holds triggered at the same time and then digitize their output later. Can
you digitize the two sample and hold outputs in the 200 uS at the 5Khz sampling rate?

 

How about 2 analog sample and holds triggered at the same time

How will that give the variable delay the TS wants with a 20KHz bandwidth?

So I don't see any solution other than the ADC/memory/DAC technique suggested by MrChips.

 

If you want 20kHz bandwidth you need at least a 44.1kHz sampling rate.
If you just read the A/D and send the data straight to the D/A that will be 22us delay.
You only need 7 words of memory, so it is not really very adjustable - only 6 possible settings: 22us, 44us, 66us, 88us etc.
If you need it more adjustable then you will need either a variable sampling rate or a higher sampling rate.

Also worth a try is PT2399 - as used in reverbs everywhere.

 

Also worth a try is PT2399

Looks like the delay from that device is a lot more than the TS wants.

 

If you use a processor with a faster A/D such as the LPC15xx or Renesas Ra4M1 or RA4M2, then you can set the delay between the two samples in the sequence.
If you sample the voltage first and arrange the delay between the samples to be 6us, haven't you solved the problem without any additional hardware?
at t=0 the voltage will be sampled. At t=6us the current will be sampled, but it will reflect the current as it was 6us ago, i.e. at t=0

 

How about 2 analog sample and holds triggered at the same time

This is one solution i thought of with a programmable delay line between the trigger of the two s/h units for phase alignment , so far this seems the best solution..

If you use a processor with a faster A/D such as the LPC15xx...

i want to use the device i am already familiar with an i have libraries for. learning another programming language and developing new libraries and routines from scratch is too onerous

Also worth a try is PT2399

as already noted this chip gives mS delays not uS so is at least 1 magnitude too slow, i need nS adjustable delays in the 150uS range

 

This is one solution i thought of with a programmable delay line between the trigger of the two s/h units for phase alignment , so far this seems the best solution..

But what about the samples you need to take during the delay time?
A 40KHz sample rate for the 20KHz signal has a 25µs time between samples, so a 150µs delay will require the sequential sample and delay of 6 samples.
It would seem you would have to use six s/h's.

 

I interpret the real problem as taking two samples at the same time at about a 5KHz rate and statistically processing them to
some sort of long term average. This implies he doesn't need to see the inbound bandwidth. He does have to worry
about his sampling point winding up in sync with the input sine and always sampling the same point in the sine
as to give him non-representative statistics.

 

I interpret the real problem as taking two samples at the same time at about a 5KHz rate and statistically processing them to
some sort of long term average. This implies he doesn't need to see the inbound bandwidth. He does have to worry
about his sampling point winding up in sync with the input sine and always sampling the same point in the sine
as to give him non-representative statistics.

Okay, I think I see what you are suggesting.
The problem I see from my understanding, is that the TS wants to delay the high frequency voltage signal to match the current signal so they can be simultaneously multiplied together, and then the lower frequency averaging is performed.
Is that not the case?

 

TS wants to delay the high frequency voltage signal to match the current signal...

exactly , i need to compensate for mismatched processing times in the voltage and current sensing branches, the current sensor takes 6us (latency) whereas the voltage scaling opamp is instantaneous so i have to delay the faster voltage branch so it matches the same point in time as the current branch

 

Is it necessary that you use an isolated current sensor?
What about measuring the voltage across a small series shunt resistor with the same type amp you use to measure the voltage?
Then the voltage and current signals should essentially be coincident.

 

Oh, just trigger one sample & hold 6 uS before the other... Then digitize both.

 

What is the frequency (range) of the signal that you are sampling?
What is this MCU that you are using which has such a slow A/D?
What accuracy are you trying to achieve? Will the delay circuit produce an end result that is more accurate than if you simply accepted the 84us delay (90us from the A/D less the 6us from the current sensor)?
Is the 6us delay from the current sensor fixed? Or (more likely) it is due to a single-pole roll-off.

 

I have feeling, that we need a diagram here
also the the frequencies / bandwidths where,

You have 20 KHz range signals, your averaging, then sampling at 5 KHz
or are you sampling the signal directly at 5 KHz , then averaging

The later is called under sampling, and is common in radio applications,
but you still need to follow Nyquist to get an accurate signal

But to do this, the analog input of the ADC has to be able to handle the higher frequencies,
which you will need to check if the adc in the microhas ( I doubt it )

 

@crutschow
using a shunt wont eliminate my delay problem as i cant sample simultaneously with the onboard adc's , i still need a deay to compensate for the read time difference of about 100uS as mentioned
@michael8
thats what im leaning toward using s/h with a programmable delay for the holdoff
@Ian
params all previously discussed as well as the mcu etc, no delay gives >70% error @20khz, delay to within 400nS of perfect sync gives 5% error, and obviously a tighter match improves this. the highest freq gives worst error. looking for at least 5% accuracy hopefully better
@Dr
yes sampling continously @ 5ish ksps and storing then averaging and processing after the sample buffer is full, as i said nyquist doesnt matter as this is a long term ave , ive already tested it and its accurate for freq even higher than the 20k target. im not needing 1 cycle resolution so the averaging over tens of thousands of cycles is accurate for repetitive waveforms. the adc is rated at 1msps so is plenty faster enough, reason for it being so slow is the circuitpython interpreter for the code on the M4 samd51 microcontroller is neutering the hardware , but its what i have to work with and try to work around