Hey Guys,

Last attempt here. I've spent hours trying to work out the Gate Drive and the Low Power Mode, but I am totally out of my depth.

I just want a reasonable circuit guesstimate as to how the FL5150 operates. But I can't work out the internals...

Here is what I have.


And the FL5150 block diagram.


Please help

 

But I can't work out the internals...

I'm not surprised. The datasheet is not particularly clear and omits much of the detail needed for successful modelling.
I'm puzzled, too, as to how the chip can be used at mains voltages when the maximum allowed voltage on the OC sense pins is only ~6V above Gnd?

 

I'm puzzled, too, as to how the chip can be used at mains voltages when the maximum allowed voltage on the OC sense pins is only ~6V above Gnd?

Because the OC sense pins are connected through 2meg resistors to the Line Hot and Load Hot. Did you not see the circuit in fig.5 on the data sheet?

But I can't work out the internals...

Why do you need to know the internals?
SG

 

Did you not see the circuit in fig.5 on the data sheet?

Yes, but its unclear what (if any) voltage dividing arrangement there is internally in the IC. There's a lot of guesswork necessary to be sure the IC is being modelled accurately.

Why do you need to know the internals?

In order to create a satisfactory Spice model.

 

In order to create a satisfactory Spice model.

Got It!

 

It doesn't need to be accurate. Not by a long shot.

I really just want the 'DRV Gate' and the 'Low Power Mode' parts working (as per my picture in the original post). Just to see roughly how it works. They both drive MOSFETs (DRV Gate drives those two back to back MOSFETs, and the Low Power Mode is a PMOS which shorts 'Vs' and 'Low Power' so no current flows through R1).

I don't really care about the OCsense or the Zero Crossing. And I already roughly have Vs and Vdd and the DIM Cntrl pins working.

It's just my understanding on how to drive MOSFETs isn't good enough to do the two parts I want. Every time I try, I get strange results with referencing things to 'Vs' and 'gnd_a'.

 

I tried the 'bipolar totem pole driver'.


But
* What are those bumps?
* Why is the Gate Drv only getting to ~4.5V? I thought the 5V pulses should cause Vs (17V) to be applied to Gate DRV...?

With a resistor between Gate-Source, I remove the bumps


But I have a capacitor in my final circuit, as per the datasheet. So this must say of something about how the internals work?

 

@Alec_t , @crutschow Any thoughts? (Sorry for the direct tag - but you guys have come through for me before).