Hello,
I am trying to design H bridge DC AC Inverter.
Here is the sinus signal(Purple line) with no load, Vin:30VDC
The PWM configuration is Modified Unipolar PWM (Fast leg 100kHz, Slow leg 50Hz), L:450uH, Cout:8,8uF
I know schematic is important I can share but what could be the reason for the sine being like this in general?

 

Hello,
I am trying to design H bridge DC AC Inverter.
Here is the sinus signal(Purple line) with no load, Vin:30VDC
The PWM configuration is Modified Unipolar PWM (Fast leg 100kHz, Slow leg 50Hz), L:450uH, Cout:8,8uF
I know schematic is important I can share but what could be the reason for the sine being like this in general?
View attachment 314005

Are you using a sine pattern or just a square wave and filtering to get a sine wave output?
Also, MOSFET's or Bipolars?

 

First, I suggest attaching a resistive load to see what effect that has. And second, provide a circuit schematic, NOT A WIRING DIAGRAM, and also, not a collection of snippets each showing one component.
ALSO, a much more detailed description of how it is supposed to be working will help a lot.

 

Hello there - it appears your software / switching pattern is changing somewhat as you move away from the zero crossing - with a bit of a discontinuity at or near the Zero Xing, if you kick an unloaded output filter - it will ring as shown, so try and keep the PWM pattern consistent, even though reactive power is flowing at light loads due to the filter ( i.e. making positive volts out but the current is into the sw node ).

 

Also - when the slow leg changes from gnd to pos bus, there is a CM ( common mode ) step induced in the output ( everything is lifted up ) - depending on how your ( earthed ? ) scope ground is connected to the secondary - you may be creating this effect with your scope ground - try a fully differential measurement, e.g. Ch1 probe tip to output, CH2 probe tip to other output - then subtract CH2 from CH1 on the scope - now only the 10M impedance ( on a x 10 probe ) is contacting any part of the output.

 

L:450uH, Cout:8,8uF

What is the ringing frequency? (the slower one)

 

2.53kHz, or ~ 400uS per cycle - which is pretty much what is observed - seems like pwrtrnx above has picked the causes

 

We can't see enough of the wave though we need to see the entire cycle or several cycles.

It may just be from the switching pattern that is why I asked about that. Read all the post not just the one you see last.

 

Hello again,
The schematic is attached. The PCB is single layer aluminum PCB.
I use application software from TIDM-2008 (Texas Instruments)
Here is the PWM Sequence:

This PWM is called modified unipolar PWM. (Fast leg 100kHz, Slow leg 50Hz)
I use resistive load and ringing has decreased. The difference can be seen in the first post.
The ringing frequency is about 3kHz if cout is 6,6uF and 2,5kHz when cout is 8,8uf.

 

Hello there - it appears your software / switching pattern is changing somewhat as you move away from the zero crossing - with a bit of a discontinuity at or near the Zero Xing, if you kick an unloaded output filter - it will ring as shown, so try and keep the PWM pattern consistent, even though reactive power is flowing at light loads due to the filter ( i.e. making positive volts out but the current is into the sw node ).

Hi,
I used symmetrical inductors as shown below;
The ringing has decreased, I will share scope screen as soon as possible, but I think this method is not the real solution.


I measured Drain- Source voltage of Q4 (Slow leg low side FET) with single inductor and with 2 two inductor:

-With single Inductor (connected between SW1 node and Cout), CH3: Q4 Drain-Source Voltage, CH1: Q4 Gate-Source



-With two Inductor (one of inductor is connected between SW1 node /Cout and the other inductor is connected to SW2 node / Cout) CH3: Q4 Drain-Source Voltage, CH1: Q4 Gate-Source, CH4: Q1 Gate-Source (Fast leg-100kHz)

 

your snubber resistors are too small

 

The waveforms do not tell us a great deal as there is no real information as to what part of the cycle they are - or what the load is

in any event some RC snubbing of the output filter would cure the ringing as it appears to be at the Fo of the filter - and caused by the slow leg, you could slow the gate drive to the slow leg as well, say 47 ohm turn on R's

( just by the by, my Co. has designed similar inverters from 100W to 100kW )

 

Also your Q1, Q2 dead time ( slow leg ) appears far too long, 1uS would be fine.

 

Also your Q1, Q2 dead time ( slow leg ) appears far too long, 1uS would be fine.

The dead zone between slow leg FET's was 170us with soft start, I cancelled soft start time then now dead zone approximately 50us. Actually I dont know why TI's application software has such a dead zone time.I'll see if I can reduce it with software.

 

Switch off times vary among devices and as "shoot thru" is quite destructive, a longer dead time as default would make sense.

 

any dead time over 500nS should be more than adequate

 

Hello again,
I've changed PWM algorithm and ringing has decreased considerably.
Vin:50VDC, CH3:- AC out, CH1: Low side FET Drain-Source voltage.