For calculating the gate current required to turn on the MOSFET, which of the following formulae is correct?
a) Ig = Qg/td(on); (Total Gate Charge) / (Turn-on delay time of MOSFET)
b) Ig = Qg/(td(on)+tr); (Total Gate Charge) / (Turn-on delay time + rise time of MOSFET)

Please post the exact formula, if none of the above ar right. Thank you

 

Think about it for a moment. You must fully charge and then discharge the capacitance charge, once for each cycle. You know Q, so the your question is just, "What is the cycle time?" I think you know the answer.

 

Think about it for a moment. You must fully charge and then discharge the capacitance charge, once for each cycle. You know Q, so the your question is just, "What is the cycle time?" I think you know the answer.

By the cycle time, did you mean time period corresponding to the switching frequency? To turn on the MOSFET we just need to charge the gate-source capacitance. I am not able to understand the significance of discharging the capacitance!

 

Gate current is not constant; it varies exponentially as the capacitance charges. Are you asking about average current? And how do you define fully charged: when Vgs(th) is reached or when the FET is switched on fully?

 

Gate current is not constant; it varies exponentially as the capacitance charges. Are you asking about average current? And how do you define fully charged: when Vgs(th) is reached or when the FET is switched on fully?

I want to select a suitable gate driver for a MOSFET. The Gate driver has a current specification. So I am looking for gate current required for turning on the MOSFET.

Please feel free to give suggestions and insights on the selection of gate drivers like what parameters to be considered. Thank you.

 

The Gate driver has a current specification.

It probably has both a peak and an average specification. You should design to stay within both specifications.

 

Usually a gate driver chip will sink more current than it will source. Like almost everything electrical a mosfet gate will only draw the amount of current it needs. More current available will help turn the mosfet on, and not hurt the gate. It's voltage that gets applied to the gate that will harm it not the current. If you apply a higher voltage than is specified in the mosfet data sheet that is what will kill the mosfet, not the current.

 

The median current equals Iav = Qg * freq,
Pulse current Ipulse_max = max (Qg/Tf, Qg/Tr)

 

For calculating the gate current required to turn on the MOSFET, which of the following formulae is correct?
a) Ig = Qg/td(on); (Total Gate Charge) / (Turn-on delay time of MOSFET)
b) Ig = Qg/(td(on)+tr); (Total Gate Charge) / (Turn-on delay time + rise time of MOSFET)

Please post the exact formula, if none of the above ar right. Thank you

Hi,

There are actually three parts of the turn on gate wave. If you dont want to use just Qgs then you have to look deeper into this. I dont have time right now but maybe later today.

 

Hello again,

I'll try to keep this simple.

First, the charge Q is in C and the current is in C/s. So we have:
I=C/s=Q/t

The total charge Q is based on both the gate to source capacitance and the gate to drain capacitance. Thus it includes the effects of both capacitances as well as the effect of the gain on the gate to drain capacitance.

The delay time would be mostly caused by the gate to source capacitance because that is happening before much has changed in the output (about 10 percent), but in any case the gate to source capacitance is already considered in the total gate charge so I=Q/t should be adequate.

I believe this quantity was developed to make it easier for designers to quickly calculate the max current that would be required to switch in a given time, but the entire response is much more interesting and informative if you get around to looking at that. It's outlined in a lot of different links online. It's a three part waveform where you can clearly see the three parts when you look at the gate signal. The first part is a sort of ramp, followed by a plateau, followed by a more or less exponential rise. Most of the delay is probably in that first ramp because nothing significant has changed on the output yet. The actual delay ends when the output has changed by about 10 percent, which means the Miller capacitance gets in there a little bit too.

I think the current source is often modeled as a pseudo linear one with I=gm*(Vg-Vth), but a better model would have a non linear gm with current Id. I might look into this a little more as it's been a long time since i had to calculate this too. Some data books like those from International Rectifier (if it is still called that) have detailed information about this if you are into that level of calculation of electrical circuits. They also go into detail about other not too often talked about 'insider' stuff like source inductance and it's actual effects on the switching waveform.

Another point real quick is, sometimes the gate resistor is made high enough such that the output back emf from inductive loads is lower than it would be with a very low gate resistor value. This is also a trick to reduce EMI but of course has to be applied very carefully because it increases power dissipation in the MOSFET.

International Rectifier also warns that not all MOSFETs are spec'd exactly the same, so some may overestimate their products switching speed based on total Q.